DS543 Datasheet, PDF (11/24 Pages) Xilinx, Inc – MOST Network Interface Controller v1.4

MOST Network Interface Controller v1.4
Ingress / Egress
Ingress and egress are defined from the reference point of the core. An ingress transaction is
synonymous with a write from the user interface to the core; an egress transaction is synonymous with
a read to the user interface from the core. Table 2 summarizes the user interface access types (as
illustrated in Figure 5), and identifies them as either ingress or egress buffers.
Table 2: Ingress / Egress Buffer Mapping
Access
Buffer Type
Word Count
RX OPB Read
Egress
Full word count
RX Streaming Read
Egress
Full word count
RX Streaming Write
Ingress
Empty word count
TX OPB Write
Ingress
Empty word count
TX Streaming Read
Egress
Full word count
TX Streaming Write
Ingress
Empty word count
Full Word Count
An interrupt is generated every time a total of C_FWC words have been filled in the egress buffer. Set-
ting the C_FWC to 8 generates an interrupt when eight words (32 bytes) have been written to the buffer
by the source. Another interrupt is generated when an additional eight words are written by the source,
or an end-of- packet is received for asynchronous data. On initialization, all egress buffers are empty,
and as a result, no interrupts are generated until the appropriate data is written.
Empty Word Count
An interrupt is generated every time a total of C_EWC have been removed in the ingress buffer. Setting
the C_EWC to 8 generates an interrupt when there is room for at least eight words (32 bytes) to be writ-
ten to the ingress buffer. When the interrupt is asserted, there is an assumption that the external proces-
sor will write eight words to the ingress buffer. In essence, eight locations of the buffer are now reserved
and no longer considered unused. When or if there are eight more unused word locations, an addi-
tional interrupt is generated.
On initialization, all ingress buffers are empty. The user application must prime the ingress buffer with
data, and then enable the logical channel. Interrupts are then generated when there is C_EWC words
free in the buffer. After the interrupt is cleared, an additional interrupt can be generated depending on
the setting of C_EWC and the number of unused word locations remaining.
OPB Support
The MOST NIC is an OPB slave. The address of the MOST NIC can be configured using the CORE Gen-
erator GUI.
Table 3: OPB Base Address Parameter
Name
Possible Values
C_BASEADDR
Valid address range:
0x00000000 - 0xffffc000,
where bits 18-31 must be 0b
Default Value
Description
h’0000_0000 Base Address for the core
DS543 September 19, 2008
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