DS543 Datasheet, PDF (18/24 Pages) Xilinx, Inc – MOST Network Interface Controller v1.4

MOST Network Interface Controller v1.4
Table 6: MOST Streaming Port Interface (Cont’d)
Signal Name
Direction
Description
STR_TI_SRC_RDY
Input
Transmit Ingress Source Ready: Write data on the STR_TI_DATA is
available and valid.
STR_TI_DST_RDY
Output
Transmit Ingress Destination Ready: The target has accepted the
write data for this logical channel (STR_TI_LC)
STR_TI_WCINT[0:3]
Output
Transmit Ingress Interrupt: Asserted for 1 clock when the transmit
ingress logical channel buffer has crossed the word count as
configured by the empty word count parameter (EWC). There is one
signal for each transmit write logical channel.
Streaming Port Receive Egress (Read from Streaming Port)
The streaming ports use LocalLink signaling, where either the core or the external requesting interface
are free to negate ready, indicating that a transmission is stalled for this cycle. Only when both source
and destination ready are asserted does a transfer occur. The user can change the logical channel at any
time as long *_DST_RDY is deasserted the previous cycle, although this can result in less than full
throughput. Typically, the number of bytes read should match four times the word count as configured
by the full word count parameter (FWC). Figure 7 illustrates two example transactions where the external
requestor stalls the access on logical channel 0, and the MOST NIC stalls the access on logical channel 1.
Figure Top x-ref 7
OPB_CLK
STR_RE_DST_RDY
STR_RE_LC
STR_RE_DATA
STR_RE_SRC_RDY
LC req 0
d0
d1 d2
LC req 1
d3
Figure 7: Receive Streaming Port Read
Streaming Port Receive Ingress (Write to Streaming Port)
The write port is similar to the read port. Typically, the number of bytes written should match four
times the word count, as configured by the empty word count parameter (EWC). An application can
watch the standard word count flags to trigger this access, or, alternatively, the hardware component
can keep accessing data from any given channel, which the core provides as long as data exists. Figure 8
illustrates sample transactions where the external requestor is stalling on logical channel 0, and the
MOST NIC is stalling on logical channel 1.
Figure Top x-ref 8
OPB_CLK
STR_RI_SRC_RDY
STR_RI_LC
STR_RI_DATA
STR_RI_DST_RDY
LC req 0
d0
d1 d2
LC req 1
d3
d4
Figure 8: Receive Streaming Port Write
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DS543 September 19, 2008