DS543 Datasheet, PDF (19/24 Pages) Xilinx, Inc – MOST Network Interface Controller v1.4

MOST Network Interface Controller v1.4
Streaming Port Transmit Egress and Ingress
The operation of the Transmit Egress streaming port is similar to the Receive Egress streaming port. The
operation of the Transmit Ingress streaming port is similar to the Receive Ingress streaming port.
Configuration Space
Table 7 defines the MOST NIC control registers, including those that support byte enables. In addition,
information about supported byte-enable locations is provided. All registers are 32-bits wide. For
detailed information about the control registers, including those located in block RAM and base
address offsets, see Chapter 6, "Configuration Space," in the MOST NIC User Guide.
Byte Enable Support
Locations that do not support byte enables ignore the OPB_BE[0:3] signals and provide 32-bit reads
and writes. Locations that support byte enables qualify writes with the assertion of OPB_BE[0:3].
Read access ignores the OPB_BE[0:3] signal and provides 32-bit read data.
Reserved Bits
Reads to write-only registers, reserved registers, and reserved bits return zero(s). Writes to any read-
only registers or bits are ignored.
Table 7: MOST Controller Registers
Name
Register
Name
Byte
Enable
Description
MOST Controller Registers
Version
VR
N Indicates capability and version information about the core.
Soft Reset
SRR
Y
Places the MOST NIC in reset mode and enables the core for active
operation.
Mode Select
MSR
Configures the operating mode of the controller. This register can be
read back in order to determine that it has been programmed
Y correctly. However, in order to determine the actual state of the core,
the Status Register (SR) must be read.Configures the operating
mode of the controller.
Status
SR
N Indicates the functional state of the MOST NIC.
Channel Control
CCR
Configures information regarding the synchronous and
asynchronous channels. Specifically, the Channel Control Register
Y
sets the boundary of the MOST frame dedicated to synchronous and
asynchronous data when a Master. This value determines the
boundary between the synchronous and asynchronous data area in
the frame. When a slave, this register is read-only.
Maximum and
Current Position
and Delay
MCPDR
Provides the maximum number of devices (position) and the
N maximum delay value of the MOST network. It also provides the
current position and delay value of the device.
Logical Address
LAR
Y Configures the logical address of this node.
Alternate
Address
AAR
Y Configures the alternate address of this node.
Group Address
GAR
Y Configures the group address of this node.
DS543 September 19, 2008
www.xilinx.com
19