DS543 Datasheet, PDF (21/24 Pages) Xilinx, Inc – MOST Network Interface Controller v1.4

MOST Network Interface Controller v1.4
Table 7: MOST Controller Registers (Cont’d)
Name
Register
Name
Byte
Enable
Description
Buffer Interrupt
Status
BISR
Contains bits that are set when a particular interrupt condition occurs.
Y If the corresponding mask bit in the Buffer Interrupt Enable Register
(BIER) is set, the BUFFER_irpt interrupt is generated.
Buffer Interrupt
Pending
BIPR
Indicates the interrupts that are actually indicated to software. In
N effect, it is bit-wise the BISR register bit ANDed with the BIER
register.
Buffer Interrupt
Enable
BIER
Y
Used to enable or disable the generation of the interrupts. Interrupts
are enabled by setting the appropriate bit in the BIER.
Buffer Interrupt
Clear
BICR
Y
Used to clear interrupt status bits. Writes of ’1’ clear the appropriate
bit in the BISR and the BIPR.
Routing Table
Common Routing
Table
CRT
Used to configure the mapping of timeslots to logical channels for
both the transmit and receive data paths of the MOST controller. The
MOST frame consists of up to 60 synchronous timeslots or
N asynchronous data. Each word in the routing table controls the
mapping of 4 timeslots. Logical channel #0 is reserved for
asynchronous data and as such can not be used for any synchronous
timeslots.
Logical Channel
Enable
LCE
Y Used to enable/disable channels on a logical channel basis.
Slave Active 1
Slave Active 2
SAR1
SAR2
N Reflects the active bits set by slave nodes during the transmission of
the Network Information Channel on the MOST Ring. Not all bits are
N ^{necessarily accurate, depending on the node’s position within the}
ring.
Master Allocation
Table
MAT
Used to read the assignments of synchronous timeslots to various
N controllers on the ring. This table is only valid when this node is a
Master.
Streaming Port MMR
Streaming Port
MMR
STR_MMR
This portion of the memory map is dedicated to external modules
Y
connected to the streaming ports. Any accesses to this portion of the
memory mapped are forwarded to the streaming port through the
Streaming Port MMR bus (STR_MMR).
MOST PLL Control Registers
PLL Reference
Count Register
PRCR
Used by the PLL clock monitoring logic to evaluate the quality of the
Y clock generated by the PLL. If a problem was detected, the core will
automatically reset the external PLL.
External PLL
Reset Count
EPRC
N Indicates the number of times reset was applied to the external PLL.
DS543 September 19, 2008
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