DS543 Datasheet, PDF (2/24 Pages) Xilinx, Inc – MOST Network Interface Controller v1.4

MOST Network Interface Controller v1.4
About the MOST NIC
MOST, a growing standard for automotive multimedia networks, is a low-cost, fiber-optic based net-
work providing integration for passenger infotainment networks. The Xilinx MOST NIC core, in con-
junction with the Xilinx automotive (XA) solution and embedded processing allows designers to
leverage the MOST open standard network by providing a higher level of customization in a scalable
and flexible design solution. The MOST NIC core is fully validated using independent system testing.
The MOST NIC core provides unique support for real-time access to the synchronous portion of the
MOST frame through the LocalLink interface (a Xilinx standardized user interface), allowing designs to
take advantage of powerful parallel-processing capabilities of the Xilinx FPGA family. The core is
delivered with a 32-bit OPB bus suitable for both standalone and embedded applications. A complete
hardware and software solution is realized when used in conjunction with a MicroBlaze soft processor
or hard PowerPC solution, drivers, and MOCEAN Network Services.
Feature Summary
The following summary identifies some of the key features of the MOST NIC core.
Master/Slave Configuration
The MOST NIC core can be configured for master/slave or slave-only mode operation. The mas-
ter/slave core can be used either as a master or as a slave depending on the user application. When
only slave functionality is required, the unused logic is automatically removed for optimal resource uti-
lization in the slave-only core.
• Master/Slave. When configured for master/slave mode, the MOST NIC core supports full-ring
master capabilities including clock generation and control message initiation. All slave operations
are also fully supported. For clock generation, an external clock source is required.
• Slave only. Slave only is typically used for the majority of MOST controllers. The slave mode
supports the transmission and reception of all MOST data types (synchronous, asynchronous, and
control). The clock is recovered from the incoming MOST stream. An external PLL is required for
clock recovery and data alignment.
Full Synchronous Channel
• The MOST frame data is received on a timeslot (or physical channel) basis. The MOST NIC
supports a range of 4-60 timeslots of synchronous data. The Synchronous Boundary Descriptor
(SBD) sets the boundary between the synchronous and asynchronous data in 4 bytes increments, or
quadlets.
• The total amount of synchronous and asynchronous data available in a frame is 60 bytes. For this
reason, the asynchronous portion of the frame is 60 bytes minus the synchronous data (60-(SBD*4)
bytes).
• The remainder of the usable data in the MOST frame (2 bytes) is reserved for control data.
2
www.xilinx.com
DS543 September 19, 2008