DS543 Datasheet, PDF (12/24 Pages) Xilinx, Inc – MOST Network Interface Controller v1.4

MOST Network Interface Controller v1.4
Core Interfaces
This section describes the interface signals of the MOST NIC core. The major MOST NIC interfaces
include the following:
• MOST Ring Interface
• Host Interface
• Streaming Port Interface
MOST NIC Interfaces
Figure 6 illustrates the MOST NIC interfaces. All signals are defined in their respective sections follow-
ing the illustration.
Figure Top x-ref 6
MOST Host
Interface
MOST Streaming
Port Interface for
Register Configuation
MOST Streaming
Port Interface for
TX Ingress
MMRs
MOST Streaming
Port Interface for
RX Ingress
TX_BUF RX_BUF
MOST Streaming
Port Interface for
TX Egress
MACs
MOST Streaming
Port Interface for
RX Egress
MOST Ring
Interface
Figure 6: MOST Core Interfaces
MOST Ring Interface
Table 4 defines the signals (MOST_) interfacing to the MOST ring via an external PHY and DCM.
Table 4: MOST Ring Interface
Signal Name
Direction
Description
MOST_TX
Output
Transmit MOST Data: The serial bit stream transmitted onto the MOST
ring.
MOST_RX
Input
Receive MOST Data: The serial bit stream received from the MOST
ring.
MOST_PLL_CLK
Input
MOST PLL Clock: The clock recovered from the external PLL.
Received data is sampled with this clock.
MOST_COM_CLK
Input
MOST Common Clock: The clock used internally to the core. For a
slave-only core, the MOST common clock can be connected to
MOST_PLL_CLK. For a master-slave core, the source when in Master
mode is the external crystal, and the source when in slave mode is
MOST_PLL_CLK.
12
www.xilinx.com
DS543 September 19, 2008