DS543 Datasheet, PDF (14/24 Pages) Xilinx, Inc – MOST Network Interface Controller v1.4

MOST Network Interface Controller v1.4
Table 5: MOST Host Interface
Signal Name
Direction
Description
System Signals
OPB_Clk
Input Clock: All host interface signals are synchronous to this clock.
OPB_Rst
Input
Reset: The MOST core is reset to the default state upon assertion of this
signal.
MOST_Irpt
Output
Interrupt: Asserted to indicate a MOST Controller Status interrupt condition
to the microprocessor or interrupt controller.
BUFFER_Irpt
Output
Interrupt: Asserted to indicate a Buffer interrupt condition to the
microprocessor or interrupt controller.
OPB Slave Request Signals
OPB_select
Input
Select: Indicates an active read or write access. This signal qualifies all bus
inputs from the OPB master.
OPB_RNW
Input
Read not Write: A logic ’1’ indicates a read access to the location address by
OPB_Abus. A logic ’0’ indicates a write access to the location addressed by
OPB_Abus.
OPB_seqAddr
Input
Sequential Transfer: Indicates that the transfer being performed will be
followed with a transfer to the next sequential address in the same direction,
read or write. For any given burst transaction, OPB_seqAddr needs to be
asserted for every address except the last
OPB_ABus[0:31]
Input
Address: Bus used to specify the address being accessed either for a read
or write.
OPB_DBus[0:31]
Input
Write Data Bus: Data to be written to the address specified by OPB_Abus.
The write is acknowledged by Sln_xferAck when complete.
OPB_BE[0:3]
Input Byte Enable: Selects which byte lane of the data bus is being accessed.
Sln_DBus[0:31]
Output
Read_Data: Data read from the address OPB_ABus. Data is valid when a
read request followed by an acknowledge (Sln_xfer Ack) is asserted.
Sln_xferAck
Output
Acknowledge: Acknowledgement of a completed read or write transfer.
Following a read request, indicates that the data on Sln_Dbus is valid.
Following a write request, indicates that the data on OPB_DBus was
accepted.
Sln_Retry
Output
Retry: Asserted to indicate the MOST core is unable to perform the transfer
requested at this time. This signal will be asserted instead of Sln_xferAck
when required. This signal is not used for this release of the core.
Sln_ToutSup
Output
Time Out Suppress: Asserted to indicate the OPB arbiter that the bus
operation will be delayed for an extended period of time. This signal is not
used for this release of the core.
Sln_ErrAck
Output
Error Acknowledge: Asserted to indicate an error was encountered during
the requested transfer. Asserted coincident with Sln_xferAck if asserted. This
signal will be asserted when a transaction forwarded to the streaming
memory map does not respond within the required time
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DS543 September 19, 2008