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XC5VLX30-1FF676I Datasheet, PDF (87/91 Pages) Xilinx, Inc – Virtex-5 FPGA DC Characteristics | |||
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Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
Date
02/02/07
Version
3.0
Revision
⢠Added XC5VSX35T, XC5VSX50T, and SX5VSX95T devices to appropriate tables.
⢠Revised the IRPU values in Table 3, page 2.
⢠Revised the ICCAUXQ values in Table 4, page 3.
⢠Added values to Table 5, page 6.
⢠Minor added notes and changed descriptions in Table 25, page 13 and Table 26, page 13.
⢠Revised the SFI-4.1 (SDR LVDS Interface) -1 values in Table 53, page 29.
⢠Revised gain error, bipolar gain error, and event conversion time in Table 51, page 26
⢠Changed the design software version that matches this data sheet above Table 54 on page 30.
⢠In Switching Characteristics, the following values are revised:
⢠LVCMOS25, Fast, 12 mA in Table 56, page 32.
⢠Setup and Hold and TICKQ in Table 60, page 40.
⢠TOCKQ in Table 61, page 41.
⢠Sequential delay values in Table 63, page 43.
⢠TCXB, TCEO, and TDICK in Table 65, page 44.
⢠TRCKO_DO, TRCKO_POINTERS, TRCKO_ECCR, TRCKO_ECC, TRCCK_ADDR, TRDCK_DI, TRDCK_DI_ECC,
TRCCK_WREN, and TRCO_FLAGS in Table 68, page 47.
⢠TDSPDCK_CC, TDSPCCK_{RSTAA, RSTBB}, TDSPCKO_{PP, CRYOUTP}, FMAX_MULT_NOMREG and
FMAX_MULT_NOMREG_PATDET in Table 69, page 48.
⢠TBCCKO_O, and TBGCKO_O in Table 71, page 53.
⢠TBUFIOCKO_O and FMAX in Table 72, page 53.
⢠TBRCKO_O and TBRCKO_O_BYP in Table 73, page 54.
⢠Parameters in Table 74, page 55 including notes.
⢠In Virtex-5 Device Pin-to-Pin Output Parameter Guidelines:
⢠Revised values in Table 84, Table 85, and Table 86.
⢠In Virtex-5 Device Pin-to-Pin Input Parameter Guidelines:
⢠Clarified description in Table 91, page 69.
⢠Revised values in Table 91, Table 92, and Table 93.
⢠Removed duplicate TBUFR_MAX_FREQ and TBUFIO_MAX_FREQ from Table 98.
⢠Revised values in Table 101, page 85.
DS202 (v5.3) May 5, 2010
www.xilinx.com
Product Specification
87
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