XC5VLX30-1FF676I Datasheet, PDF (22/91 Pages) Xilinx, Inc – Virtex-5 FPGA DC Characteristics

Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
GTX_DUAL Tile Switching Characteristics
Consult UG198:Virtex-5 FPGA RocketIO GTX Transceiver User Guide for further information.
Table 42: GTX_DUAL Tile Performance
Symbol
Description
F_GTXMAX
F_GPLLMAX
F_GPLLMIN
Maximum GTX transceiver data rate
Maximum PLL frequency
Minimum PLL frequency
Speed Grade
-3
-2
-1
6.5
6.5
4.25
3.25
3.25
3.25
1.48
1.48
1.48
Units
Gb/s
GHz
GHz
Table 43: Dynamic Reconfiguration Port (DRP) in the GTX_DUAL Tile Switching Characteristics
Symbol
Description
Speed Grade
-3
-2
-1
F_GTXDRPCLK GTX DCLK (DRP clock) maximum frequency
200
175
150
Units
MHz
Table 44: GTX_DUAL Tile Reference Clock Switching Characteristics
Symbol
Description
F_GCLK
T_RCLK
T_FCLK
T_DCREF
T_GJTT
Reference clock frequency range⁽¹⁾
Reference clock rise time
Reference clock fall time
Reference clock duty cycle
Reference clock total jitter ^{(2, 3)}
T_LOCK
T_PHASE
Clock recovery frequency acquisition
time
Clock recovery phase acquisition time
Conditions
CLK
20% – 80%
80% – 20%
CLK
At 100 KHz
At 1 MHz
Initial PLL lock
Lock to data after PLL has
locked to the reference clock
All Speed Grades
Min
Typ
Max
60
650
200
200
40
50
60
–145
–150
0.25
1
200
Units
MHz
ps
ps
%
dBc/Hz
dBc/Hz
ms
µs
Notes:
1. GREFCLK can be used for serial bit rates up to 1 Gb/s; however, Jitter Specifications are not guaranteed when using GREFCLK.
2. GTX_DUAL jitter characteristics measured using a clock with specification T_GJTT. A reference clock with higher phase noise can be used
with link margin trade off.
3. The selection of the reference clock is application dependent. This parameter describes the quality of the reference clock used during
transceiver jitter characterization - see Table 46 and Table 47.
X-Ref Target - Figure 10
80%
T_RCLK
20%
T_FCLK
ds202_05_100506
Figure 10: Reference Clock Timing Parameters
DS202 (v5.3) May 5, 2010
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Product Specification
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