XC5VLX30-1FF676I Datasheet, PDF (68/91 Pages) Xilinx, Inc – Virtex-5 FPGA DC Characteristics

Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
Table 90: Global Clock Input to Output Delay With DCM and PLL in Source-Synchronous Mode
Symbol
Description
Device
Speed Grade
-3
-2
-1
LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with DCM and PLL
in Source-Synchronous Mode
T_{ICKOFDCM0_PLL} Global Clock and OUTFF with DCM and PLL
XC5VLX20T
XC5VLX30
N/A
3.66
4.11
3.37
3.63
4.06
XC5VLX30T
3.37
3.63
4.06
XC5VLX50
3.39
3.65
4.08
XC5VLX50T
3.39
3.65
4.08
XC5VLX85
3.52
3.78
4.20
XC5VLX85T
3.52
3.78
4.20
XC5VLX110
3.57
3.84
4.27
XC5VLX110T
3.57
3.84
4.27
XC5VLX155
3.83
4.10
4.53
XC5VLX155T
3.83
4.10
4.53
XC5VLX220
N/A
4.33
4.76
XC5VLX220T
N/A
4.33
4.76
XC5VLX330
N/A
4.50
4.95
XC5VLX330T
N/A
4.50
4.95
XC5VSX35T
3.55
3.81
4.24
XC5VSX50T
3.57
3.83
4.26
XC5VSX95T
N/A
4.08
4.50
XC5VSX240T
N/A
4.57
5.02
XC5VTX150T
N/A
3.99
4.42
XC5VTX240T
N/A
4.22
4.65
XC5VFX30T
3.66
3.97
4.41
XC5VFX70T
3.59
3.88
4.32
XC5VFX100T
3.74
4.02
4.44
XC5VFX130T
3.91
4.21
4.65
XC5VFX200T
N/A
4.52
4.94
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
2. DCM and PLL output jitter are already included in the timing calculation.
DS202 (v5.3) May 5, 2010
www.xilinx.com
Product Specification
68