XC5VLX30-1FF676I Datasheet, PDF (60/91 Pages) Xilinx, Inc – Virtex-5 FPGA DC Characteristics

Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
Output Clock Jitter
Table 79: Output Clock Jitter
Symbol
Description
Clock Synthesis Period Jitter
T_{PERJITT_0}
T_{PERJITT_90}
T_{PERJITT_180}
T_{PERJITT_270}
T_{PERJITT_2X}
T_{PERJITT_DV1}
T_{PERJITT_DV2}
T_{PERJITT_FX}
CLK0
CLK90
CLK180
CLK270
CLK2X, CLK2X180
CLKDV (integer division)
CLKDV (non-integer division)
CLKFX, CLKFX180
Notes:
1. Values for this parameter are available in the Architecture Wizard.
Constraints
Speed Grade
-3
-2
-1
Units
±120 ±120 ±120
ps
±120 ±120 ±120
ps
±120 ±120 ±120
ps
±120 ±120 ±120
ps
±200 ±200 ±230
ps
±150 ±150 ±180
ps
±300 ±300 ±345
ps
Note 1 Note 1 Note 1 ps
Output Clock Phase Alignment
Table 80: Output Clock Phase Alignment
Symbol
Description
Constraints
Speed Grade
-3
-2
-1
Units
Phase Offset Between CLKIN and CLKFB
T_{IN_FB_OFFSET}
CLKIN/CLKFB
Phase Offset Between Any DCM Outputs⁽¹⁾
±50
±50
±60
ps
T_{OUT_OFFSET_1X}
T_{OUT_OFFSET_2X}
T_{OUT_OFFSET_FX}
Duty Cycle Precision⁽²⁾
T_{DUTY_CYC_DLL}
T_{DUTY_CYC_FX}
CLK0, CLK90, CLK180, CLK270
CLK2X, CLK2X180, CLKDV
CLKFX, CLKFX180
DLL outputs⁽³⁾
DFS outputs⁽⁴⁾
±140 ±140 ±160
ps
±150 ±150 ±200
ps
±160 ±160 ±220
ps
±150 ±150 ±180
ps
±150 ±150 ±180
ps
Notes:
1. All phase offsets are in respect to group CLK1X.
2. CLKOUT_DUTY_CYCLE_DLL applies to the 1X clock outputs (CLK0, CLK90, CLK180, and CLK270) only if
DUTY_CYCLE_CORRECTION = TRUE. The duty cycle distortion includes the global clock tree (BUFG).
3. DLL Outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
4. DFS Outputs are used in these instances to describe the outputs: CLKFX and CLKFX180.
DS202 (v5.3) May 5, 2010
www.xilinx.com
Product Specification
60