XC5VLX30-1FF676I Datasheet, PDF (82/91 Pages) Xilinx, Inc – Virtex-5 FPGA DC Characteristics

Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
Table 97: Global Clock Setup and Hold With DCM and PLL in Source-Synchronous Mode
Symbol
T_{PSDCMPLL_0}/
T_{PHDCMPLL_0}
Description
Device
No Delay Global Clock and IFF⁽²⁾ with DCM and
PLL in Source-Synchronous Mode
XC5VTX150T
XC5VTX240T
Speed Grade
-3
-2
-1
N/A
0.40
0.40
0.89
0.94
N/A
0.38
0.39
1.12
1.17
XC5VFX30T
0.34
0.36
0.37
0.83
0.87
0.92
XC5VFX70T
0.29
0.32
0.32
0.75
0.78
0.83
XC5VFX100T
0.35
0.35
0.35
0.90
0.92
0.96
XC5VFX130T
0.33
0.37
0.41
1.07
1.11
1.16
XC5VFX200T
N/A
0.29
0.33
1.42
1.46
Units
ns
ns
ns
ns
ns
ns
ns
Notes:
1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the
Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global
Clock input signal using the fastest process, lowest temperature, and highest voltage. The timing values were measured using the fine-phase
adjustment feature of the DCM. These measurements include CMT jitter; DCM CLK0 driving PLL, PLL CLKOUT0 driving BUFG. Package
skew is not included in these measurements.
2. IFF = Input Flip-Flop.
DS202 (v5.3) May 5, 2010
www.xilinx.com
Product Specification
82