XC5VLX30-1FF676I Datasheet, PDF (7/91 Pages) Xilinx, Inc – Virtex-5 FPGA DC Characteristics

Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
SelectIO™ DC Input and Output Levels
Values for V_IL and V_IH are recommended input voltages. Values for I_OL and I_OH are guaranteed over the recommended
operating conditions at the V_OL and V_OH test points. Only selected standards are tested. These are chosen to ensure that
all standards meet their specifications. The selected standards are tested at a minimum V_CCO with the respective V_OL and
V_OH voltage levels shown. Other standards are sample tested.
Table 7: SelectIO DC Input and Output Levels
I/O Standard
V, Min
V_IL
V, Max
V_IH
V, Min
V, Max
V_OL
V, Max
V_OH
V, Min
I_OL
I_OH
mA
mA
LVTTL
–0.3
0.8
2.0
3.45
0.4
2.4
Note(3) Note(3)
LVCMOS33,
LVDCI33
–0.3
0.8
2.0
3.45
0.4
V_CCO – 0.4 Note(3) Note(3)
LVCMOS25,
LVDCI25
–0.3
0.7
1.7
V_CCO + 0.3
0.4
V_CCO – 0.4 Note(3) Note(3)
LVCMOS18,
LVDCI18
–0.3
35% V_CCO
65% V_CCO
V_CCO + 0.3
0.45
V_CCO – 0.45 Note(4) Note(4)
LVCMOS15,
LVDCI15
–0.3
35% V_CCO
65% V_CCO
V_CCO + 0.3 25% V_CCO 75% V_CCO Note(4) Note(4)
LVCMOS12
PCI33_3⁽⁵⁾
PCI66_3⁽⁵⁾
PCI-X⁽⁵⁾
GTLP
GTL
HSTL I_12
HSTL I⁽²⁾
HSTL II⁽²⁾
HSTL III⁽²⁾
HSTL IV⁽²⁾
DIFF HSTL I⁽²⁾
DIFF HSTL II⁽²⁾
SSTL2 I
SSTL2 II
DIFF SSTL2 I
DIFF SSTL2 II
SSTL18 I
SSTL18 II
DIFF SSTL18 I
DIFF SSTL18 II
–0.3
–0.2
–0.2
–0.2
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
35% V_CCO
30% V_CCO
30% V_CCO
35% V_CCO
V_REF – 0.1
V_REF – 0.05
V_REF – 0.1
V_REF – 0.1
V_REF – 0.1
V_REF – 0.1
V_REF – 0.1
50% V_CCO – 0.1
50% V_CCO – 0.1
V_REF – 0.15
V_REF – 0.15
50%
V_CCO – 0.15
50%
V_CCO – 0.15
V_REF – 0.125
V_REF – 0.125
50%
V_CCO – 0.125
50%
V_CCO – 0.125
65% V_CCO
50% V_CCO
50% V_CCO
50% V_CCO
V_REF + 0.1
V_REF + 0.05
V_REF + 0.1
V_REF + 0.1
V_REF + 0.1
V_REF + 0.1
V_REF + 0.1
50% V_CCO + 0.1
50% V_CCO + 0.1
V_REF + 0.15
V_REF + 0.15
50%
V_CCO + 0.15
50%
V_CCO + 0.15
V_REF + 0.125
V_REF + 0.125
50%
V_CCO + 0.125
50%
V_CCO + 0.125
V_CCO + 0.3
V_CCO
V_CCO
V_CCO
–
–
V_CCO + 0.3
V_CCO + 0.3
V_CCO + 0.3
V_CCO + 0.3
V_CCO + 0.3
V_CCO + 0.3
V_CCO + 0.3
V_CCO + 0.3
V_CCO + 0.3
V_CCO + 0.3
V_CCO + 0.3
V_CCO + 0.3
V_CCO + 0.3
V_CCO + 0.3
V_CCO + 0.3
25% V_CCO
10% V_CCO
10% V_CCO
10% V_CCO
0.6
0.4
25% V_CCO
0.4
0.4
0.4
0.4
–
–
V_TT – 0.61
V_TT – 0.81
–
–
V_TT – 0.47
V_TT – 0.60
–
–
75% V_CCO
90% V_CCO
90% V_CCO
90% V_CCO
N/A
N/A
75% V_CCO
V_CCO – 0.4
V_CCO – 0.4
V_CCO – 0.4
V_CCO – 0.4
–
–
V_TT + 0.61
V_TT + 0.81
–
Note(6)
Note(5)
Note(5)
Note(5)
36
32
6.3
8
16
24
48
–
–
8.1
16.2
–
Note(6)
Note(5)
Note(5)
Note(5)
N/A
N/A
6.3
–8
–16
–8
–8
–
–
–8.1
–16.2
–
–
–
–
V_TT + 0.47
V_TT + 0.60
–
6.7
–6.7
13.4 –13.4
–
–
–
–
–
Notes:
1. Tested according to relevant specifications.
2. Applies to both 1.5V and 1.8V HSTL.
3. Using drive strengths of 2, 4, 6, 8, 12, 16, or 24 mA.
4. Using drive strengths of 2, 4, 6, 8, 12, or 16 mA.
5. For more information on PCI33_3, PCI66_3, and PCI-X, refer to UG190: Virtex-5 FPGA User Guide, Chapter 6, 3.3V I/O Design Guidelines.
6. Supported drive strengths of 2, 4, 6, or 8 mA.
DS202 (v5.3) May 5, 2010
www.xilinx.com
Product Specification
7