XC5VLX30-1FF676I Datasheet, PDF (41/91 Pages) Xilinx, Inc – Virtex-5 FPGA DC Characteristics

Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
Table 61: OLOGIC Switching Characteristics
Symbol
Description
Setup/Hold
T_ODCK/T_OCKD
D1/D2 pins Setup/Hold with respect to CLK
T_OOCECK/T_OCKOCE OCE pin Setup/Hold with respect to CLK
T_OSRCK/T_OCKSR
SR/REV pin Setup/Hold with respect to CLK
T_OTCK/T_OCKT
T1/T2 pins Setup/Hold with respect to CLK
T_OTCECK/T_OCKTCE
TCE pin Setup/Hold with respect to CLK
Combinatorial
T_DOQ
Sequential Delays
T_OCKQ
T_RQ
T_GSRQ
Set/Reset
T_RPW
D1 to OQ out or T1 to TQ out
CLK to OQ/TQ out
SR/REV pin to OQ/TQ out
Global Set/Reset to Q outputs
Minimum Pulse Width, SR/REV inputs
Speed Grade
-3
-2
-1
Units
0.30
0.36
0.44
ns
–0.21 –0.21 –0.21
0.16
0.19
0.23
ns
–0.07 –0.07 –0.07
0.93
1.02
1.16
ns
–0.20 –0.20 –0.20
0.28
0.34
0.41
ns
–0.18 –0.18 –0.18
0.20
0.23
0.29
ns
–0.06 –0.06 –0.06
0.62
0.70
0.83
ns
0.61
0.62
0.62
ns
1.63
1.89
2.27
ns
7.30
7.30
10.10
ns
0.80
0.98
1.25 ns, Min
DS202 (v5.3) May 5, 2010
www.xilinx.com
Product Specification
41