XC5VLX30-1FF676I Datasheet, PDF (17/91 Pages) Xilinx, Inc – Virtex-5 FPGA DC Characteristics

Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
Table 33: GTP_DUAL Tile User Clock Switching Characteristics⁽¹⁾
Symbol
Description
F_TXOUT
F_RXREC
T_RX
T_RX2
TXOUTCLK maximum frequency
RXRECCLK maximum frequency
RXUSRCLK maximum frequency
RXUSRCLK2 maximum frequency
T_TX
T_TX2
TXUSRCLK maximum frequency
TXUSRCLK2 maximum frequency
Conditions
RXDATAWIDTH = 0
RXDATAWIDTH = 1
TXDATAWIDTH = 0
TXDATAWIDTH = 1
Speed Grade
-3
-2
-1
375
375
320
375
375
320
375
375
320
350
350
320
187.5
187.5
160
375
375
320
350
350
320
187.5
187.5
160
Notes:
1. Clocking must be implemented as described in UG196: Virtex-5 FPGA RocketIO GTP Transceiver User Guide
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Table 34: GTP_DUAL Tile Transmitter Switching Characteristics
Symbol
Description
Min
Typ
F_GTPTX
T_RTX
T_FTX
T_LLSKEW
V_TXOOBVDPP
T_TXOOBTRANS
T_J3.75
D_J3.75
T_J3.2
D_J3.2
T_J2.5
D_J2.5
T_J2.0
D_J2.0
T_J1.25
D_J1.25
T_J1.00
D_J1.00
T_J500
D_J500
T_J100
D_J100
Serial data rate range
TX Rise time
TX Fall time
TX lane-to-lane skew⁽¹⁾
Electrical idle amplitude
Electrical idle transition time
Total Jitter⁽²⁾
Deterministic Jitter⁽²⁾
Total Jitter⁽²⁾
Deterministic Jitter⁽²⁾
Total Jitter⁽²⁾
Deterministic Jitter⁽²⁾
Total Jitter⁽²⁾
Deterministic Jitter⁽²⁾
Total Jitter⁽²⁾
Deterministic Jitter⁽²⁾
Total Jitter⁽²⁾
Deterministic Jitter⁽²⁾
Total Jitter⁽²⁾
Deterministic Jitter⁽²⁾
Total Jitter⁽²⁾
Deterministic Jitter⁽²⁾
0.1
140
120
3.75 Gb/s
3.20 Gb/s
2.50 Gb/s
2.00 Gb/s
1.25 Gb/s
1.00 Gb/s
500 Mb/s
100 Mb/s
Notes:
1. Using same REFCLK input with TXENPMAPHASEALIGN enabled for up to four consecutive GTP_DUAL sites.
2. Using PLL_DIVSEL_FB = 2, INTDATAWIDTH = 1.
3. All jitter values are based on a Bit-Error Ratio of 1e^–12.
Max
F_GTPMAX
855
20
40
0.35
0.19
0.35
0.19
0.30
0.14
0.30
0.14
0.20
0.10
0.20
0.10
0.10
0.04
0.02
0.01
Units
Gb/s
ps
ps
ps
mV
ns
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
DS202 (v5.3) May 5, 2010
www.xilinx.com
Product Specification
17