XC5VLX30-1FF676I Datasheet, PDF (48/91 Pages) Xilinx, Inc – Virtex-5 FPGA DC Characteristics

Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
Table 68: Block RAM and FIFO Switching Characteristics (Cont’d)
Symbol
Description
Speed Grade
-3
-2
-1
Units
Reset Delays
T_{RCO_FLAGS}
Maximum Frequency
Reset RST to FIFO Flags/Pointers⁽¹¹⁾
1.10
1.26
1.48 ns, Max
F_MAX
F_{MAX_CASCADE}
F_{MAX_FIFO}
F_{MAX_ECC}
Block RAM in all modes
Block RAM in cascade configuration
FIFO in all modes
Block RAM and FIFO in ECC configuration
550
500
450
MHz
500
450
400
MHz
550
500
450
MHz
415
375
325
MHz
Notes:
1. TRACE will report all of these parameters as T_{RCKO_DO}.
2. T_{RCKO_DOR} includes T_{RCKO_DOW}, T_{RCKO_DOPR}, and T_{RCKO_DOPW} as well as the B port equivalent timing parameters.
3. These parameters also apply to synchronous FIFO with DO_REG = 0.
4. T_{RCKO_DO} includes T_{RCKO_DOP} as well as the B port equivalent timing parameters.
5. These parameters also apply to multirate (asynchronous) and synchronous FIFO with DO_REG = 1.
6. T_{RCKO_FLAGS} includes the following parameters: T_{RCKO_AEMPTY}, T_{RCKO_AFULL}, T_{RCKO_EMPTY}, T_{RCKO_FULL}, T_{RCKO_RDERR}, T_{RCKO_WRERR.}
7. T_{RCKO_POINTERS} includes both T_{RCKO_RDCOUNT} and T_{RCKO_WRCOUNT.}
8. The ADDR setup and hold must be met when EN is asserted even though WE is deasserted. Otherwise, block RAM data corruption is possible.
9. T_{RCKO_DI} includes both A and B inputs as well as the parity inputs of A and B.
10. These parameters also apply to RDEN.
11. T_{RCO_FLAGS} includes the following flags: AEMPTY, AFULL, EMPTY, FULL, RDERR, WRERR, RDCOUNT, and WRCOUNT.
DSP48E Switching Characteristics
Table 69: DSP48E Switching Characteristics
Symbol
Description
Setup and Hold Times of Data/Control Pins to the Input Register Clock
TDSPDCK_{AA, BB, ACINA, BCINB}/
TDSPCKD_{AA, BB, ACINA, BCINB}
{A, B, ACIN, BCIN} input to {A, B}
register CLK
TDSPDCK_CC/TDSPCKD_CC
C input to C register CLK
Setup and Hold Times of Data Pins to the Pipeline Register Clock
TDSPDCK_{AM, BM, ACINM, BCINM}/
TDSPCKD_{AM, BM, ACINM, BCINM}
{A, B, ACIN, BCIN} input to M register
CLK
Setup and Hold Times of Data/Control Pins to the Output Register Clock
TDSPDCK_{AP, BP, ACINP, BCINP}_M/
TDSPCKD_{AP, BP, ACINP, BCINP}_M
{A, B, ACIN, BCIN} input to P register
CLK using multiplier
TDSPDCK_{AP, BP, ACINP, BCINP}_NM/
TDSPCKD_{AP, BP, ACINP, BCINP}_NM
{A, B, ACIN, BCIN} input to P register
CLK not using multiplier
TDSPDCK_CP/TDSPCKD_CP
C input to P register CLK
TDSPDCK_{PCINP, CRYCINP, MULTSIGNINP}/
TDSPCKD_{PCINP, CRYCINP, MULTSIGNINP}
Setup and Hold Times of the CE Pins
TDSPCCK_{CEA1A, CEA2A, CEB1B, CEB2B}/
TDSPCKC_{CEA1A, CEA2A, CEB1A, CEB2B}
TDSPCCK_CECC/TDSPCKC_CECC
{PCIN, CARRYCASCIN, MULTSIGNIN}
input to P register CLK
{CEA1, CEA2A, CEB1B, CEB2B} input
to {A, B} register CLK
CEC input to C register CLK
Speed
-3
-2
-1
0.17 0.21 0.26
0.17 0.23 0.30
0.14 0.16 0.20
0.26 0.31 0.37
1.30 1.44 1.71
0.19 0.19 0.19
2.39
–0.30
1.35
–0.10
1.30
–0.13
1.06
0.11
2.74
–0.30
1.54
–0.10
1.42
–0.13
1.17
0.11
3.25
–0.30
1.83
–0.10
1.70
–0.13
1.31
0.11
0.24 0.28 0.33
0.21 0.25 0.31
0.19 0.21 0.26
0.17 0.21 0.28
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
DS202 (v5.3) May 5, 2010
www.xilinx.com
Product Specification
48