XC5VLX30-1FF676I Datasheet, PDF (44/91 Pages) Xilinx, Inc – Virtex-5 FPGA DC Characteristics

Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
Input/Output Delay Switching Characteristics
Table 64: Input/Output Delay Switching Characteristics
Symbol
Description
IDELAYCTRL
T_{IDELAYCTRLCO_RDY}
F_{IDELAYCTRL_REF}
IDELAYCTRL_REF_PRECISION
T_{IDELAYCTRL_RPW}
IODELAY
T_{IDELAYRESOLUTION}
T_{IDELAYPAT_JIT}
T_{IODELAY_CLK_MAX}
T_{IODCCK_CE} / T_{IODCKC_CE}
Reset to Ready for IDELAYCTRL
REFCLK frequency
REFCLK precision
Minimum Reset pulse width
IODELAY Chain Delay Resolution
Pattern dependent period jitter in delay chain
for clock pattern
Pattern dependent period jitter in delay chain
for random data pattern (PRBS 23)
Maximum frequency of CLK input to IODELAY
CE pin Setup/Hold with respect to CK
T_{IODCK_INC}/ T_{IODCKC_INC}
INC pin Setup/Hold with respect to CK
T_{IODCK_RST}/ T_{IODCKC_RST}
RST pin Setup/Hold with respect to CK
T_{IODDO_T}
TSCONTROL delay to MUXE/MUXF switching
and through IODELAY
T_{IODDO_IDATAIN}
T_{IODDO_ODATAIN}
Propagation delay through IODELAY
Propagation delay through IODELAY
Notes:
1. Average Tap Delay at 200 MHz = 78 ps.
2. Units in ps, peak-to-peak per tap, in High Performance mode.
3. Delay depends on IODELAY tap setting. See TRACE report for actual values.
CLB Switching Characteristics
Table 65: CLB Switching Characteristics
Symbol
Description
Combinatorial Delays
T_ILO
An – Dn LUT address to A
An – Dn LUT address to AMUX/CMUX
An – Dn LUT address to BMUX_A
T_ITO
T_AXA
T_AXB
T_AXC
T_AXD
T_BXB
T_BXD
An – Dn inputs to A – D Q outputs
AX inputs to AMUX output
AX inputs to BMUX output
AX inputs to CMUX output
AX inputs to DMUX output
BX inputs to BMUX output
BX inputs to DMUX output
Speed Grade
-3
-2
-1
Units
3.00
200.00
±10
50.00
3.00
200.00
±10
50.00
3.00
200.00
±10
50.00
µs
MHz
MHz
ns
1/(64 x F_REF x 1e⁶)⁽¹⁾
0
0
0
±5
±5
±5
300
0.29
–0.06
0.18
0.02
0.25
–0.12
Note 3
250
0.34
–0.06
0.20
0.04
0.28
–0.12
Note 3
250
0.42
–0.06
0.24
0.06
0.33
–0.12
Note 3
Note 3
Note 3
Note 3
Note 3
Note 3
Note 3
ps
Note 2
Note 2
MHz
ns
ns
ns
Speed Grade
-3
-2
-1
Units
0.08
0.09
0.10
ns, Max
0.20
0.22
0.25
ns, Max
0.31
0.35
0.40
ns, Max
0.67
0.77
0.90
ns, Max
0.39
0.44
0.53
ns, Max
0.46
0.52
0.61
ns, Max
0.31
0.36
0.42
ns, Max
0.55
0.62
0.73
ns, Max
0.36
0.41
0.48
ns, Max
0.45
0.51
0.59
ns, Max
DS202 (v5.3) May 5, 2010
www.xilinx.com
Product Specification
44