XC5VLX30-1FF676I Datasheet, PDF (65/91 Pages) Xilinx, Inc – Virtex-5 FPGA DC Characteristics

Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
Table 87: Global Clock Input to Output Delay With PLL in System-Synchronous Mode
Symbol
Description
Device
Speed Grade
-3
-2
-1
Units
LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with PLL in System-Synchronous Mode
T_ICKOFPLL
Global Clock and OUTFF with PLL
XC5VLX20T
XC5VLX30
N/A
2.36
2.73
ns
2.03
2.30
2.70
ns
XC5VLX30T
2.03
2.30
2.70
ns
XC5VLX50
2.20
2.47
2.86
ns
XC5VLX50T
2.20
2.47
2.86
ns
XC5VLX85
2.21
2.49
2.88
ns
XC5VLX85T
2.21
2.49
2.88
ns
XC5VLX110
2.25
2.53
2.92
ns
XC5VLX110T
2.25
2.53
2.92
ns
XC5VLX155
2.34
2.60
3.01
ns
XC5VLX155T
2.34
2.60
3.01
ns
XC5VLX220
N/A
2.74
3.12
ns
XC5VLX220T
N/A
2.74
3.12
ns
XC5VLX330
N/A
2.89
3.27
ns
XC5VLX330T
N/A
2.89
3.27
ns
XC5VSX35T
2.02
2.28
2.62
ns
XC5VSX50T
2.12
2.36
2.76
ns
XC5VSX95T
N/A
2.29
2.69
ns
XC5VSX240T
N/A
2.96
3.34
ns
XC5VTX150T
N/A
2.54
2.92
ns
XC5VTX240T
N/A
2.67
3.04
ns
XC5VFX30T
2.44
2.67
3.06
ns
XC5VFX70T
2.48
2.71
3.10
ns
XC5VFX100T
2.41
2.70
3.10
ns
XC5VFX130T
2.48
2.75
3.17
ns
XC5VFX200T
N/A
2.96
3.35
ns
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
2. PLL output jitter is included in the timing calculation.
DS202 (v5.3) May 5, 2010
www.xilinx.com
Product Specification
65