XC5VLX30-1FF676I Datasheet, PDF (69/91 Pages) Xilinx, Inc – Virtex-5 FPGA DC Characteristics

Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
Virtex-5 Device Pin-to-Pin Input Parameter Guidelines
All devices are 100% functionally tested. The representative values for typical pin locations and normal clock loading are
listed in Table 91. Values are expressed in nanoseconds unless otherwise noted.
Table 91: Global Clock Setup and Hold Without DCM or PLL
Symbol
Description
Device
Speed Grade
-3
-2
-1
Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard.⁽¹⁾
T_PSFD/ T_PHFD
Full Delay (Legacy Delay or Default Delay)
Global Clock and IFF⁽²⁾ without DCM or PLL
XC5VLX20T
N/A
1.63
1.86
–0.41 –0.41
XC5VLX30
1.49
–0.35
1.60
–0.35
1.77
–0.35
XC5VLX30T
1.49
–0.35
1.60
–0.35
1.76
–0.35
XC5VLX50
1.48
–0.30
1.59
–0.30
1.76
–0.30
XC5VLX50T
1.48
–0.30
1.59
–0.30
1.76
–0.30
XC5VLX85
1.75
–0.49
1.89
–0.49
2.09
–0.49
XC5VLX85T
1.75
–0.49
1.89
–0.49
2.09
–0.49
XC5VLX110
1.74
–0.43
1.88
–0.43
2.09
–0.43
XC5VLX110T
1.73
–0.43
1.88
–0.43
2.09
–0.43
XC5VLX155
2.06
–0.50
2.36
–0.50
2.78
–0.49
XC5VLX155T
2.06
–0.50
2.36
–0.50
2.78
–0.49
XC5VLX220
N/A
2.57
2.86
–0.74 –0.74
XC5VLX220T
N/A
2.57
2.86
–0.74 –0.74
XC5VLX330
N/A
2.55
2.85
–0.56 –0.56
XC5VLX330T
N/A
2.57
2.86
–0.56 –0.56
XC5VSX35T
1.47
–0.16
1.59
–0.16
1.76
–0.16
XC5VSX50T
1.62
–0.31
1.74
–0.31
1.93
–0.31
XC5VSX95T
N/A
2.10
2.32
–0.44 –0.44
XC5VSX240T
N/A
2.01
2.28
0.18
0.18
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DS202 (v5.3) May 5, 2010
www.xilinx.com
Product Specification
69