XC5VLX30-1FF676I Datasheet, PDF (26/91 Pages) Xilinx, Inc – Virtex-5 FPGA DC Characteristics

Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
System Monitor Analog-to-Digital Converter Specification
Table 51: Analog-to-Digital Specifications
Parameter
Symbol
Comments/Conditions
Min Typ Max
AV_DD = 2.5V ± 2%, V_REFP = 2.5V, V_REFN = 0V, ADCCLK = 5.2 MHz, T_A = T_MIN to T_MAX, Typical values at T_A=+25°C
DC Accuracy: All external input channels such as V_P/V_N and V_AUXP[15:0]/V_AUXN[15:0], Unipolar Mode,
and Common Mode = 0V
Resolution
10
Integral Nonlinearity
INL
±2
Differential Nonlinearity
Unipolar Offset Error⁽¹⁾
Bipolar Offset Error⁽¹⁾
Gain Error⁽¹⁾
Bipolar Gain Error⁽¹⁾
DNL
No missing codes (T_MIN to T_MAX)
Guaranteed Monotonic
Uncalibrated
Uncalibrated measured in bipolar mode
Uncalibrated
Uncalibrated measured in bipolar mode
±0.9
±2
±30
±2
±30
±0.2
±2
±0.2
±2
Total Unadjusted Error
(Uncalibrated)
Total Unadjusted Error
(Calibrated)
Calibrated Gain Temperature
Coefficient
TUE
TUE
Deviation from ideal transfer function.
V_REFP – V_REFN = 2.5V
Deviation from ideal transfer function.
V_REFP – V_REFN = 2.5V
Variation of FS code with temperature
±10
±1
±2
±0.01
DC Common-Mode Reject
CMRR_DC V_N = V_CM = 0.5V ± 0.5V,
70
V_P – V_N = 100mV
Conversion Rate⁽²⁾
Conversion Time - Continuous
Conversion Time - Event
T/H Acquisition Time
DRP Clock Frequency
t_CONV
t_CONV
t_ACQ
DCLK
Number of CLK cycles
Number of CLK cycles
Number of CLK cycles
DRP clock frequency
26
32
21
4
8
250
ADC Clock Frequency
ADCCLK Derived from DCLK
1
5.2
CLK Duty cycle
Analog Inputs⁽³⁾
40
60
Dedicated Analog Inputs
Input Voltage Range
V_P - V_N
Unipolar Operation
Differential Inputs
Unipolar Common Mode Range (FS input)
0
–0.25
0
1
+0.25
+0.5
Differential Common Mode Range (FS input) +0.3
+0.7
Bandwidth
20
Auxiliary Analog Inputs
Input Voltage Range
V_AUXP[0] /V_AUXN[0] to V_AUXP[15]
/V_AUXN[15]
Unipolar Operation
Differential Operation
Unipolar Common Mode Range (FS input)
Differential Common Mode Range (FS input)
0
–0.25
0
+0.3
1
+0.25
+0.5
+0.7
Bandwidth
10
Input Leakage Current
A/D not converting, ADCCLK stopped
±1.0
Input Capacitance
10
On-chip Supply Monitor Error
On-chip Temperature Monitor
Error
V_CCINT and V_CCAUX with calibration enabled
–40°C to +125°C with calibration enabled
±1.0
±4
Units
Bits
LSBs
LSBs
LSBs
LSBs
%
%
LSBs
LSBs
LSB/°C
dB
MHz
MHz
%
Volts
MHz
Volts
kHz
µA
pF
% Reading
°C
DS202 (v5.3) May 5, 2010
www.xilinx.com
Product Specification
26