XC5VLX30-1FF676I Datasheet, PDF (57/91 Pages) Xilinx, Inc – Virtex-5 FPGA DC Characteristics

Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DCM Switching Characteristics
Table 76: Operating Frequency Ranges for DCM in Maximum Speed (MS) Mode
Symbol
Description
Speed Grade
-3
-2
-1
Units
Outputs Clocks (Low Frequency Mode)
F_1XLFMSMIN
CLK0, CLK90, CLK180, CLK270
F_1XLFMSMAX
F_2XLFMSMIN
CLK2X, CLK2X180
F_2XLFMSMAX
F_DVLFMSMIN
CLKDV
F_DVLFMSMAX
F_FXLFMSMIN
CLKFX, CLKFX180
F_FXLFMSMAX
Input Clocks (Low Frequency Mode)
F_DLLLFMSMIN
CLKIN (using DLL outputs)^{(1, 3, 4)}
F_DLLLFMSMAX
F_{CLKINLFFXMSMIN}
CLKIN (using DFS outputs only)^{(2, 3, 4)}
F_{CLKINLFFXMSMAX}
F_PSCLKLFMSMIN
PSCLK
F_PSCLKLFMSMAX
Outputs Clocks (High Frequency Mode)
32.00
150.00
64.00
300.00
2.0
100.00
32.00
180.00
32.00
135.00
64.00
270.00
2.0
90.00
32.00
160.00
32.00
120.00
64.00
240.00
2.0
80.00
32.00
140.00
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
32.00
150.00
1.00
180.00
1.00
550.00
32.00
135.00
1.00
160.00
1.00
500.00
32.00
120.00
1.00
140.00
1.00
450.00
MHz
MHz
MHz
MHz
KHz
MHz
F_1XHFMSMIN
F_1XHFMSMAX
F_2XHFMSMIN
F_2XHFMSMAX
F_DVHFMSMIN
F_DVHFMSMAX
F_FXHFMSMIN
F_FXHFMSMAX
Input Clocks (High Frequency Mode)
F_DLLHFMSMIN
F_DLLHFMSMAX
F_{CLKINHFFXMSMIN}
F_{CLKINHFFXMSMAX}
F_PSCLKHFMSMIN
F_PSCLKHFMSMAX
CLK0, CLK90, CLK180, CLK270
CLK2X, CLK2X180
CLKDV
CLKFX, CLKFX180
CLKIN (using DLL outputs)^{(1, 3, 4)}
CLKIN (using DFS outputs only)^{(2, 3, 4)}
PSCLK
120.00
550.00
240.00
550.00
7.5
366.67
140.00
400.00
120.00
500.00
240.00
500.00
7.5
333.34
140.00
375.00
120.00
450.00
240.00
450.00
7.5
300.00
140.00
350.00
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
120.00
550.00
25.00
400.00
1.00
550.00
120.00
500.00
25.00
375.00
1.00
500.00
120.00
450.00
25.00
350.00
1.00
450.00
MHz
MHz
MHz
MHz
KHz
MHz
Notes:
1. DLL outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
2. DFS outputs are used in these instances to describe the outputs: CLKFX and CLKFX180.
3. When using the DCMs CLKIN_DIVIDE_BY_2 attribute these values should be doubled. Other resources can limit the maximum input
frequency.
4. When using a CLKIN frequency > 400 MHz and the DCMs CLKIN_DIVIDE_BY_2 attribute, the CLKIN duty cycle must be within ±5% (45/55
to 55/45).
DS202 (v5.3) May 5, 2010
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Product Specification
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