XC5VLX30-1FF676I Datasheet, PDF (54/91 Pages) Xilinx, Inc – Virtex-5 FPGA DC Characteristics

Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
Table 73: Regional Clock Switching Characteristics (BUFR)
Symbol
Description
Devices
T_{BRCKO_O}
T_{BRCKO_O_BYP}
T_{BRDO_CLRO}
Maximum Frequency
F_MAX
LX20T
LX30, LX30T, LX50, LX50T,
LX85, LX85T, LX110, LX110T,
SX35T, SX50T, FX100T, and
FX130T
Clock to out delay from
I to O
FX30T
FX70T
LX155 and LX155T
LX220, LX220T, LX330,
LX330T, SX95T, SX240T,
TX150T, TX240T, and FX200T
LX20T
Clock to out delay from I to
O with Divide Bypass
attribute set
LX30, LX30T, LX50, LX50T,
LX85, LX85T, LX110, LX110T,
SX35T, SX50T, FX30T, FX70T,
FX100T, and FX130T
LX155 and LX155T
LX220, LX220T, LX330,
LX330T, SX95T, SX240T,
TX150T, TX240T, and FX200T
Propagation delay from All
CLR to O
Regional clock tree
All
(BUFR)
Speed Grade
-3
-2
-1
N/A
0.79
0.90
0.56
0.59
0.67
0.72
0.78
0.86
0.69
0.74
0.83
0.73
0.80
0.90
N/A
0.59
0.67
N/A
0.29
0.30
0.23
0.24
0.26
0.24
0.26
0.30
N/A
0.24
0.26
0.61
0.70
0.82
300
250
250
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
DS202 (v5.3) May 5, 2010
www.xilinx.com
Product Specification
54