TH58NS100DC Datasheet, PDF (4/43 Pages) Toshiba Semiconductor – TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 1 - GBIT (128M X 8 BITS) CMOS NAND E2PROM ( 128M BYTE SmartMediaTM )

TH58NS100DC
AC CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS
(Ta = 0° to 55°C, V_CC = 3.3 V ± 0.3 V)
SYMBOL
PARAMETER
t_CLS
t_CLH
t_CS
t_CH
t_WP
t_ALS
t_ALH
t_DS
t_DH
t_WC
t_WH
t_WW
t_RR
t_RP
t_RC
t_REA
t_CEH
t_REAID
t_OH
t_RHZ
t_CHZ
t_REH
t_IR
t_RSTO
t_CSTO
t_RHW
t_WHC
t_WHR
t_AR1
t_CR
t_R
t_WB
t_AR2
t_RB
CLE Setup Time
CLE Hold Time
CE Setup Time
CE Hold Time
Write Pulse Width
ALE Setup Time
ALE Hold Time
Data Setup Time
Data Hold Time
Write Cycle Time
WE High Hold Time
WP High to WE Low
Ready to RE Falling Edge
Read Pulse Width
Read Cycle Time
RE Access Time (Serial Data Access)
CE High Time for Last Address in Serial Read Cycle
RE Access Time (ID Read)
Data Output Hold Time
RE High to Output High Impedance
CE High to Output High Impedance
RE High Hold Time
Output-High-impedance-to- RE Rising Edge
RE Access Time (Status Read)
CE Access Time (Status Read)
RE High to WE Low
WE High to CE Low
WE High to RE Low
ALE Low to RE Low (ID Read)
CE Low to RE Low (ID Read)
Memory Cell Array to Starting Address
WE High to Busy
ALE Low to RE Low (Read Cycle)
RE Last Clock Rising Edge to Busy (in Sequential Read)
t_CRY CE High to Ready (When interrupted by CE in Read Mode)
t_RST Device Reset Time (Read/Program/Erase)
MIN
MAX
UNIT
0
¾
ns
10
¾
ns
0
¾
ns
10
¾
ns
25
¾
ns
0
¾
ns
10
¾
ns
20
¾
ns
10
¾
ns
50
¾
ns
15
¾
ns
100
¾
ns
20
¾
ns
35
¾
ns
50
¾
ns
¾
35
ns
100
¾
ns
¾
35
ns
10
¾
ns
¾
30
ns
¾
20
ns
15
¾
ns
0
¾
ns
¾
35
ns
¾
45
ns
0
¾
ns
30
¾
ns
30
¾
ns
100
¾
ns
100
¾
ns
¾
25
ms
¾
200
ns
50
¾
ns
¾
200
ns
1+
¾
ms
t_r ( RY/BY )
¾
6/10/500
ms
NOTES
(2)
(1) (2)
AC TEST CONDITIONS
PARAMETER
Input level
Input pulse rise and fall time
Input comparison level
Output data comparison level
Output load
CONDITION
2.4 V, 0.4 V
3 ns
1.5 V, 1.5 V
1.5 V, 1.5 V
C_L (100 pF) + 1 TTL
2001-03-21 4/43