TH58NS100DC Datasheet, PDF (12/43 Pages) Toshiba Semiconductor – TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 1 - GBIT (128M X 8 BITS) CMOS NAND E2PROM ( 128M BYTE SmartMediaTM )

Sequential Read (3) Timing Diagram
CLE
TH58NS100DC
CE
WE
ALE
RE
I/O1
to I/O8
50H
RY/BY
A0
to A7
A9
to
A16
A17
to
A24
A25
to
A26
527
512 513 514 527
Column
Page
address address
t_{R 512 + 512 + 512 +}
t_R
N
M
N N+1 N+2
Page M
access
Page M + 1
access
: V_IH or V_IL
2001-03-21 12/43