TH58NS100DC Datasheet, PDF (22/43 Pages) Toshiba Semiconductor – TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 1 - GBIT (128M X 8 BITS) CMOS NAND E2PROM ( 128M BYTE SmartMediaTM )

TH58NS100DC
Table 3. Command table (HEX)
First Cycle Second Cycle Acceptable while Busy
Serial Data Input
80
¾
Read Mode (1)
00
¾
Read Mode (2)
01
¾
Read Mode (3)
50
¾
Reset
FF
¾
Q
Auto Program (True)
10
¾
Auto Program (Dummy)
11
¾
Auto Program
(Multi Block Program)
15
¾
Auto Block Erase
60
D0
Status Read (1)
70
¾
Q
Status Read (2)
71
¾
Q
ID Read (1)
90
¾
ID Read (2)
91
¾
HEX data bit assignment
(Example)
Serial Data Input: 80H
10000000
I/O8 7 6 5 4 3 2 I/O1
Once the device has been set to Read mode by a 00H, 01H or 50H command, additional Read commands are
not needed for sequential page Read operations.
Table 4 shows the operation states for Read mode.
Table 4. Read mode operation states
CLE
ALE
CE
WE
RE
I/O1 to I/O8
Power
Output Select
L
L
L
H
L
Output
Active
Output Deselect
L
L
L
H
H
High impedance
Active
Standby
L
L
H
H
*
High impedance
Standby
H: V_IH, L: V_IL, *: V_IH or V_IL
2001-03-21 22/43