TH58NS100DC Datasheet, PDF(38/43 Page) Toshiba Semiconductor – TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 1 - GBIT (128M X 8 BITS) CMOS NAND E2PROM ( 128M BYTE SmartMediaTM )

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TH58NS100DC Datasheet, PDF (38/43 Pages) Toshiba Semiconductor – TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 1 - GBIT (128M X 8 BITS) CMOS NAND E2PROM ( 128M BYTE SmartMediaTM )

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TH58NS100DC

(10) Note regarding the WP signal

The Erase and Program operations are automatically reset when WP goes Low. The operations are

enabled and disabled as follows:

Enable Programming

DIN

RY/BY

tWW (100 ns min)

Disable Programming

DIN

RY/BY

tWW (100 ns min)

Enable Erasing

DIN

RY/BY

tWW (100 ns min)

Disable Erasing

DIN

RY/BY

tWW (100 ns min)

2001-03-21 38/43

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