TH58NS100DC Datasheet, PDF (35/43 Pages) Toshiba Semiconductor – TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 1 - GBIT (128M X 8 BITS) CMOS NAND E2PROM ( 128M BYTE SmartMediaTM )

TH58NS100DC
(6) Addressing for program operation
Within a block, the pages must be programmed consecutively from the LSB (least significant bit) page of
the block to MSB (most significant bit) page of the block. Random page address programming is prohibited.
From the LSB page to MSB page
DATA IN: Data (1)
Data (32)
Data register
Ex.) Random page program (Prohibition)
DATA IN: Data (1)
Data (32)
Data register
Page 0
(1)
Page 1
(2)
Page 2
(3)
Page 0
(2)
Page 1
(16)
Page 2
(3)
Page 15
(16)
Page 15
(1)
Page 31
(32)
Page 31
(32)
Figure 17. page programming within a block
(7) Status Read during a Read operation
command
00
00
[A]
70
CE
WE
RY/BY
RE
Address N
Status Read
command input
Status Read
Status output
Figure 18.
The device status can be read out by inputting the Status Read command “70H” in Read mode.
Once the device has been set to Status Read mode by a “70H” command, the device will not return to Read
mode.
Therefore, a Status Read during a Read operation is prohibited.
However, when the Read command “00H” is input during [A], Status mode is reset and the device returns
to Read mode. In this case, data output starts automatically from address N and address input is
unnecessary
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