TH58NS100DC Datasheet, PDF(31/43 Page) Toshiba Semiconductor – TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 1 - GBIT (128M X 8 BITS) CMOS NAND E2PROM ( 128M BYTE SmartMediaTM )

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TH58NS100DC Datasheet, PDF (31/43 Pages) Toshiba Semiconductor – TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 1 - GBIT (128M X 8 BITS) CMOS NAND E2PROM ( 128M BYTE SmartMediaTM )

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TH58NS100DC

Reset

The Reset mode stops all operations. For example, in the case of a Program or Erase operation the internally

generated voltage is discharged to 0 volts and the device enters Wait state.

The response to an âFFHâ Reset command input during the various device operations is as follows:

When a Reset (FFH) command is input during programming

Figure 8.

Internal VPP

RY/BY

tRST (max 10 ms)

When a Reset (FFH) command is input during erasing

Internal erase

voltage

Figure 9.

RY/BY

tRST (max 500 ms)

When a Reset (FFH) command is input during Read operation

Figure 10.

RY/BY

tRST (max 6 ms)

When a Status Read command (70H) is input after a Reset

RY/BY

Figure 11.

I/O status: Pass/Fail Â® Pass

Ready/Busy Â® Ready

RY/BY

When two or more Reset commands are input in succession

(1)

I/O status: Ready/Busy Â® Busy

Figure 12.

(2)

(3)

RY/BY

The second FF command is invalid, but the third FF command is valid.

2001-03-21 31/43

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