TH58NS100DC Datasheet, PDF (24/43 Pages) Toshiba Semiconductor – TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 1 - GBIT (128M X 8 BITS) CMOS NAND E2PROM ( 128M BYTE SmartMediaTM )

TH58NS100DC
Read Mode (3)
Read mode (3) has the same timing as Read modes (1) and (2) but is used to access information in the extra
16-byte redundancy area of the page. The start pointer is therefore set to a value between byte 512 and byte
527.
CLE
CE
WE
ALE
RE
RY/BY
Busy
I/O
50H
A0 to
512 ^A3
527
Figure 5. Read mode (3) operation
Addresses bits A0 to A3 are used to set the start pointer for
the redundant memory cells, while A4 to A7 are ignored.
Once a “50H” command has been issued, the pointer moves to
the redundant cell locations and only those 16 cells can be
addressed, regardless of the value of the A4-to-A7 address.
(A “00H” command is necessary to move the pointer back to
the 0-to-511 main memory cell location.)
Sequential Read (1) (2) (3)
This mode allows the sequential reading of pages without additional address input.
00H
01H
50H
Address input
t_R
RY/BY
(00H)
0
Busy
527
Data output
(01H) 256
t_R
Busy
527
A
A
Data output
t_R
(50H)
Busy
512 527
A
Sequential Read (1)
Sequential Read (2)
Sequential Read (3)
Sequential Read modes (1) and (2) output the contents of addresses 0 to 527 as shown above, while Sequential
Read mode (3) outputs the contents of the redundant address locations only.
When the page address reaches the next block address, read command (00H/01H/50H) and address inputs are
needed.
2001-03-21 24/43