TH58NS100DC Datasheet, PDF(18/43 Page) Toshiba Semiconductor – TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 1 - GBIT (128M X 8 BITS) CMOS NAND E2PROM ( 128M BYTE SmartMediaTM )

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TH58NS100DC Datasheet, PDF (18/43 Pages) Toshiba Semiconductor – TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 1 - GBIT (128M X 8 BITS) CMOS NAND E2PROM ( 128M BYTE SmartMediaTM )

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Multi Block Erase Timing Diagram

CLE

tCLS

tCS

tCLH

tCLS

ALE

tALS

tALH

tWB

tBERASE

I/O1

to I/O8

tDS tDH

60H

A9 to A17 to A25 to

A16 A24 A26

D0H

RY/BY

Auto Block

Erase Setup

command

Erase Start

command

Busy

Max 4 times repeat

: VIH or VIL

: Do not input data while data is being output.

TH58NS100DC

71H

Status

output

Status Read

command

2001-03-21 18/43

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