TH58NS100DC Datasheet, PDF(39/43 Page) Toshiba Semiconductor – TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 1 - GBIT (128M X 8 BITS) CMOS NAND E2PROM ( 128M BYTE SmartMediaTM )

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TH58NS100DC Datasheet, PDF (39/43 Pages) Toshiba Semiconductor – TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 1 - GBIT (128M X 8 BITS) CMOS NAND E2PROM ( 128M BYTE SmartMediaTM )

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(11) When five address cycles are input

Although the device may read in a fifth address, it is ignored inside the chip.

Read operation

CLE

TH58NS100DC

ALE

I/O

RY/BY

00H, 01H or 50H

Address input

ignored

WE Internal read operation starts when WE goes High in the fourth cycle.

Figure 22.

Program operation

CLE

ALE

I/O

80H

Address input

Figure 23.

ignored

Data input

2001-03-21 39/43

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