English
Language : 

TH58NS100DC Datasheet, PDF (10/43 Pages) Toshiba Semiconductor – TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 1 - GBIT (128M X 8 BITS) CMOS NAND E2PROM ( 128M BYTE SmartMediaTM )
◁
Read Cycle (2) Timing Diagram
CLE
CE
tCLS
tCS
tCLH
tCH
TH58NS100DC
WE
tALH
tALS
tALH
ALE
RE
I/O1
to I/O8
RY/BY
tDS tDH
01H
tR
tWB
tDS tDH
A0 to A7
A9
to A16
Column address
N*
A17 A25
to A24 to A26
*: Read operation using 01H command N: 0 to 255
tAR2
tRR tRC
tREA
DOUT
DOUT
DOUT
256 + N 256 + N + 1 527
: VIH or VIL
Read Cycle (3) Timing Diagram
CLE
CE
tCLS
tCS
tCLH
tCH
WE
tALH
tALS
tALH
ALE
RE
I/O1
to I/O8
RY/BY
tDS tDH
50H
tR
tWB
tDS tDH
A0 to A7
A9
to A16
A17
to A24
A25
to A26
Column address
N*
*: Read operation using 50H command N: 0 to 15
tAR2
tRR tRC
tREA
DOUT
DOUT
DOUT
512 + N 512 + N + 1 527
: VIH or VIL
2001-03-21 10/43
 ▷