TH58NS100DC Datasheet, PDF (2/43 Pages) Toshiba Semiconductor – TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 1 - GBIT (128M X 8 BITS) CMOS NAND E2PROM ( 128M BYTE SmartMediaTM )

BLOCK DIAGRAM
I/O1
I/O8
CE
CLE
ALE
WE
RE
WP
RY/BY
I/O control circuit
Logic control
RY/BY
Status register
Address register
Command register
Control circuit
HV generator
TH58NS100DC
V_CC V_SS
Column buffer
Column decoder
Data register
Sense amp
Memory cell array
extended area
(embedded ID)
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
V_CC
Power Supply Voltage
V_IN
Input Voltage
V_I/O
Input/Output Voltage
P_D
Power Dissipation
T_stg
Storage Temperature
T_opr
Operating Temperature
RATING
-0.6 to 4.6
-0.6 to 4.6
-0.6 V to V_CC + 0.3 V (£ 4.6 V)
0.3
-20 to 65
0 to 55
CAPACITANCE *(Ta = 25°C, f = 1 MHz)
SYMBOL
PARAMETER
CONDITION
MIN
C_IN
Input
V_IN = 0 V
¾
C_OUT
Output
V_OUT = 0 V
¾
* This parameter is periodically sampled and is not tested for every device.
MAX
50
50
UNIT
V
V
V
W
°C
°C
UNIT
pF
pF
000707EBA2
· The products described in this document are subject to the foreign exchange and foreign trade laws.
· The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by
TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its
use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or
others.
· The information contained herein is subject to change without notice.
2001-03-21 2/43