TH58NS100DC Datasheet, PDF (11/43 Pages) Toshiba Semiconductor – TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 1 - GBIT (128M X 8 BITS) CMOS NAND E2PROM ( 128M BYTE SmartMediaTM )

Sequential Read (1) Timing Diagram
CLE
TH58NS100DC
CE
WE
ALE
RE
I/O1
to I/O8
00H
RY/BY
A0 A9 A17 A25
to to to to
A7 A16 A24 A26
N N + 1 N + 2 527
012
527
Column
Page
address address
t_R
t_R
N
M
Page M
access
Page M + 1
access
: V_IH or V_IL
Sequential Read (2) Timing Diagram
CLE
CE
WE
ALE
RE
I/O1
to I/O8
01H
RY/BY
A0 A9 A17 A25
to to to to
A7 A16 A24 A26
527
012
527
Column
Page
address address
t_{R 256 + 256 + 256 +}
t_R
N
M
N N+1 N+2
Page M
access
Page M + 1
access
: V_IH or V_IL
2001-03-21 11/43