TLFD500 Datasheet, PDF (9/38 Pages) Texas Instruments – 3.3 V INTEGRATED G.LITE ANALOG FRONT END

TLFD500PN
3.3 V INTEGRATED G.LITE ANALOG FRONT END
detailed description (continued)
SLAS207B – JUNE 1999 – REVISED MAY 2000
Table 1. SDR LSB Control Function
CONTROL BIT D0
0
1
CONTROL BIT FUNCTION
No secondary transfer requested
Secondary transfer requested
primary transfer data mapping
The data bit mapping of a primary transfer is shown in Figure 3. Bits D2–D15 of the SDR data stream are DAC
data. D1 is the control bit for the DGPO pin. The value written to this bit is reflected on the DGPO pin. See the
timing diagram in Figures 5 and 6 for detailed timing information. D0 is the secondary transfer request bit. When
a 1 is written to this bit, the host is requesting a secondary data transfer.
In the SDX data stream, D2–D15 contain the ADC conversion data. D0 and D1 can be set to reflect the values
of GPIO1 and GPIO2. To set D0 and D1 to reflect the GPIO values, the proper bit in the MCR register needs
to be set.
Data to CODEC
DGPO Bit
Secondary
Transfer
Request
SDR
D15 – D2
Data from CODEC
D1
D0
GPIOx Status if Configured as
Input. Zero if GPIOx Configured
as output or if Masked Off
SDX
D15 – D2
GPIO1
GPIO0
Figure 3. Primary Transfer Data Bit Mapping
secondary transfer data mapping
Secondary serial communication is used to configure the device. The data bit mapping for a secondary transfer
is shown in Figure 4. Bits D10–D14 of the SDR data from the host contain the address of the control register
involved in the transfer. D15 is a R/W bit. To read out the control register by the host processor, bit R/W must
be set to 1. To write to the control register by the host processor, bit R/W must be set to 0. During a read operation,
bits D0–D7 are don’t care. For a write operation, bits D0–D7 contain the data for the register addressed by
D10–D14. The eight bits of SDX always reflect the status of GPI00–7.
If the secondary transfer is a read operation, the contents of the control register addressed by D10–D14 of the
SDR data are reflected in bits D0–D7 of the SDX data stream. If the secondary transfer is a write operation, bits
D0–D7 on SDX will be all zeroes.
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