TLFD500 Datasheet, PDF (14/38 Pages) Texas Instruments – 3.3 V INTEGRATED G.LITE ANALOG FRONT END

TLFD500PN
3.3 V INTEGRATED G.LITE ANALOG FRONT END
SLAS207B – JUNE 1999 – REVISED MAY 2000
detailed description (continued)
register programming
The codec registers are listed in Table 2, with each bit of each register defined. All registers are 8-bit wide.
NOTE:
Bits not defined in the table are reserved for future use. During a read, the reserved bit read value
is not guaranteed. During a write, only zeroes can be written to reserved bits.
Table 2. Codec Registers
REGISTER
NAME
ADDRESS
A4 A3 A2 A1 A0
MODE
FUNCTION
BCR
00001
R/W D0: Power-down RX HP filter 1
D1: Power-down RX HP filter 2
D2: Bypass TX digital HP filter
D3: Echo mode: Echo SDR data back to SDX
D4: Reserved
D5: Reserved
D6: Reserved
PCR-RX1
00010
R/W D[5:0] = RXPGA3[5:0]; Fine gain, 0 to 9 dB, 0.25-dB steps
PCR-RX2
00011
R/W D[2:0] = RXPGA1[2:0]; 0 to 12dB, 3-dB steps
D[4:3] = RXPGA2[1:0]; 0 to 18 dB, 6-dB steps
PCR-TX
00100
R/W D[4:0] = TX PAA[4:0]; 0 to –24dB, –1-dB steps
EQR
00101
R/W D[2:0] = EQ[2:0] 0 to 25 dB, 5 dB/MHz steps; D[6:4] = EQ_PGA[2:0] 0 to 6 dB, 1 dB
steps
VCR-M
00110
R/W D[7:0] = VCXO DAC control Bit[11:4].
VCR-L
00111
R/W D[3:0] = VCXO DAC control Bit[3:0]. D[7:4] must always be zero.
GPR-C
01000
R/W D[7:0] = GPIO1 I/O control (0 = output, 1 = input)
GPR-D
01001
R/W D[7:0] = GPIO data register
Reserved
01010
R/W For future use. Read or write of register not allowed.
AUXR
01011
R/W D0: Enable auxiliary amplifier 2
D1: Enable auxiliary amplifier 1
D2: Enable auxiliary amplifier 3
D3: Enable auxiliary amplifier 4
NCO_DEF
01100
R/W D[7:0] = Default NCO divide number
NCO_DIV_DELAY
01101
R/W D[7:0] = Number of samples, from current secondary transfer, after which effect of delta
will occur.
NCO_DELTA
01110
R/W D[7:4] = Delta from default for first sample of data frame (–8 through 7)
D[3:0] = Number of times NCO divider remains changed from default before being set
back to default (0 through 15)
MCR
01111
R/W D0: S/W Power-down main reference
D1: S/W Power-down TX channel with reference still on
D2: S/W Power-down RX channel with reference still on
D3: S/W Power-down VCXO with reference still on
D4: S/W Reset
D5: Analog loop back (refer to block diagram)
D6: Digital loop back (refer to block diagram)
D7: Enable GPIO 1 and 2 to show in SDX primary data
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