TLFD500 Datasheet, PDF (4/38 Pages) Texas Instruments – 3.3 V INTEGRATED G.LITE ANALOG FRONT END

TLFD500PN
3.3 V INTEGRATED G.LITE ANALOG FRONT END
SLAS207B – JUNE 1999 – REVISED MAY 2000
Terminal Functions
TERMINAL
NAME
I/O
NO.
DESCRIPTION
AMP1INP– AMP4INP
11,2,66,59 I Auxiliary amplifier 1–4 positive input
AMP1INM– AMP4INM
10,3,65,60 I Auxiliary amplifier 1–4 negative input
AMP1OUTP– AMP2OUTP
9,4
O Auxiliary amplifier 1–2 positive output. Outputs are self-biased to AVDD_TX/2.
AMP3OUTP– AMP4OUTP
64, 61
O Auxiliary amplifier 3–4 positive output. Outputs are self-biased to AVDD_RX/2.
AMP1OUTM– AMP2OUTM
12,1
O Auxiliary amplifier 1–2 negative output. Outputs are self-biased to AVDD_TX/2.
AMP3OUTM– AMP4OUTM 67,62
O Auxiliary amplifier 3–4 negative output. Outputs are self-biased to AVDD_RX/2.
AVDD_REF
47
I Analog supply for reference circuit
AVDD_RX
48,68
I RX channel analog supply
AVDD_TX
7
I TX channel analog supply
AVSS_REF
44
I Analog supply return for reference(analog ground)
AVSS_RX
49,69
I RX channel analog supply return (analog ground)
AVSS_TX
8
I TX channel analog supply return (analog ground)
COMPDAC1
COMPDAC2
16
I TX channel decoupling cap input A. Add 1 µF capacitor to AVDD_TX
15
I TX channel decoupling cap input B. Add 1 µF capacitor to AVDD_TX
DGPO
35
O Direct general-purpose output. This pin reflects the last value written to the DGPO bit
location in the SDR data stream. It is a general-purpose output that does not require a
secondary transfer to control.
DVDD
31,39
I Digital power supply
DVDD_IO
32
I Digital I/O buffer supply
DVDD_RX
51
I RX channel digital supply
DVSS
34,40,41 I Digital ground
DVSS_IO
33
I Digital I/O buffer supply return (digital ground)
DVSS_RX
52,54,55,
56,57
I RX channel digital supply return (digital ground)
FSX
22
O Serial port frame sync transmit signal
FSR
21
O Serial port frame sync receive signal
GPIO0–GPIO7
23–30 I/O General-purpose I/O
HPF1INP
78
I RX channel stage 1 amplifier positive input. Input signal needs to have AVDD_RX/2
common mode voltage.
HPF1INM
77
I RX channel stage 1 amplifier negative input. Input signal needs to have AVDD_RX/2
common mode voltage.
HPF2INP
74
I RX channel stage 2 positive input. Input signal need to have AVDD_RX/2 common mode
voltage.
HPF2INM
73
I RX channel stage 2 negative input. Input signal need to have AVDD_RX/2 common mode
voltage.
HPF1OUTP
76
O RX channel stage 1 amplifier positive output. Used to connect external components to obtain
stage 1 HPF.
HPF1OUTM
79
O RX channel stage 1 amplifier negative output. Used to connect external components to
obtain stage 1 HPF.
HPF2OUTP
72
O RX channel stage 2 positive output. Output signal has AVDD_RX/2 common mode voltage.
HPF2OUTM
75
O RX channel stage 2 negative output. Output signal has AVDD_RX/2 common mode voltage.
MCLKIN/PLLCLKIN
37
I Multiplexed pin based on value of PLLSEL. Selects master clock input, or clock input for PLL
mode.
4
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