TLFD500 Datasheet, PDF (20/38 Pages) Texas Instruments – 3.3 V INTEGRATED G.LITE ANALOG FRONT END

TLFD500PN
3.3 V INTEGRATED G.LITE ANALOG FRONT END
SLAS207B – JUNE 1999 – REVISED MAY 2000
EQR – equalizer slope and gain control register
Address: 00101b
D7
Reserved
D6
EQPGA[2]
Contents at reset: 00000000b
D5
D4
D3
EQPGA[1] EQPGA[0] Reserved
D2
EQ[2]
D1
EQ[1]
D0
EQ[0]
Table 7. EQR Slope and Gain
D7 D6 D5 D4 D3 D2 D1 D0 HEX VALUE
BIT NAME
DESCRIPTION
R
–
–
–
–
–
–
–
–
Reserved
Bit reserved for future use
–
0
0
0
–
–
–
–
0x00
EQPGA[2:0]
0dB
–
0
0
1
–
–
–
–
0x10
1dB
–
0
1
0
–
–
–
–
0x20
2dB
–
0
1
1
–
–
–
–
0x30
3dB
–
1
0
0
–
–
–
–
0x40
4dB
–
1
0
1
–
–
–
–
0x50
5dB
–
1
1
0
–
–
–
–
0x60
6dB
–
1
1
1
–
–
–
–
0x70
INVALID
–
–
–
–
R
–
–
–
–
Reserved
Bit reserved for future use
–
–
–
–
–
0
0
0
0x00
EQ[2:0]
0dB slope
–
–
–
–
–
0
0
1
0x01
5dB slope
–
–
–
–
–
0
1
0
0x02
10dB slope
–
–
–
–
–
0
1
1
0x03
15dB slope
–
–
–
–
–
1
0
0
0x04
20dB slope
–
–
–
–
–
1
0
1
0x05
25dB slope
–
–
–
–
–
1
1
0
0x06
INVALID
–
–
–
–
–
1
1
1
0x07
INVALID
NOTES: 6. The formula to convert bit value to EQPGA gain in dB is
EQPGA gain (in dB) = EQPGA[2:0] (in decimal) x 1 dB
Similarly one can compute the EQPGA[2:0] bit combination needed, given the gain in dB.
7. The formula to convert bit value to EQ slope in dB is
EQ slope (in dB/MHz) =EQ[2:0] (in decimal) x 5 dB/MHz
Similarly one can compute the EQ[2:0] bit combination needed, given the slope in dB/MHz.
CAUTION:
Performance of the codec for invalid combination of bits is not guaranteed and such
combinations should not be used. The user should make no assumption that the code bits
will saturate to a maximum or minimum value or wrap around to a valid combination.
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