TLFD500 Datasheet, PDF (8/38 Pages) Texas Instruments – 3.3 V INTEGRATED G.LITE ANALOG FRONT END

TLFD500PN
3.3 V INTEGRATED G.LITE ANALOG FRONT END
SLAS207B – JUNE 1999 – REVISED MAY 2000
clock control – DPLL mode
As an alternative to the VCXODAC and VCXO, an off-chip crystal oscillator (XO) followed by an on-chip digital
PLL are also implemented. Refer to Figure 7 for an internal function block diagram. The input clock (35.328
MHz) goes to a programmable frequency divider to generate sampling clock for the ADC and DAC converters.
By changing the divide ratio, the phase of the sampling clock can be adjusted. Setting PLLSEL (pin 42) high
will enable the DPLL mode. Refer to DPLL section for detail.
clock generation
The clock generation block creates the necessary internal and external clocks needed by the device. All the
clocks generated are produced from the CLKIN signal.
The following are recommended operational parameters for the external VCXO:
3.3-V supply, 35.328 MHz ±50 PPM center frequency, and input control voltage range of 0 V–3 V.
The recommended duty cycle is 50/50.
clock generation – SCLK
SCLK is an output and is used for serial data transfer. It runs at 35.328 MHz. Although SCLK and MCLK run
at the same speed, there is no fixed phase relationship between them.
serial interface
The serial interface on the TLFD500PN connects directly to TI’s C54x or C6x families of DSPs. The interface
operates at 35.328 MHz. The serial port consists of five signals: SCLK, FSX, FSR, SDX, and SDR. A typical
connection diagram is shown in Figure 2.
DSP
TLFD500PN
CLKR
CLKX
FSX
FSR
DX
DR
SCLK
FSR
FSX
SDR
SDX
Figure 2. Typical Serial Port Connection
The serial port utilizes a primary/secondary scheme to transfer conversion data and control register data. A
primary transfer scheme, used to transfer conversion data, occurs every conversion period. A secondary
transfer scheme, used to transfer control data, happens only when requested by the host processor. The host
processor requests a secondary transfer by using the LSB of the SDR data of the primary scheme. A value of
1 indicates a secondary transfer request. Once the secondary request is made and the primary transfer has
been completed, secondary frame sync pulse (FSX/FSR) are transmitted to the host processor to indicate the
beginning of the secondary transfer. The secondary FSX signal arrives 16 SCLKs after the primary FSX, and
thus 48 SCLKs after the host processor request. This is because the span between FSX pulses for primary
transfers is always 32 SCLKs. Each bit is read/written at the rising edge of the SCLK clock. Data bit mappings
and example data transfers are shown in Table 1.
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