TLFD500 Datasheet, PDF (13/38 Pages) Texas Instruments – 3.3 V INTEGRATED G.LITE ANALOG FRONT END

TLFD500PN
3.3 V INTEGRATED G.LITE ANALOG FRONT END
SLAS207B – JUNE 1999 – REVISED MAY 2000
detailed description (continued)
general purpose I/O port (GPIO)
The general-purpose I/O port provides eight input/output pins and one output-only pin for control of external
circuitry, or for reading the status of external devices. The eight input/output pins are labeled GPIO0 –GPIO7.
The output-only pin is labeled DGPO (direct general-purpose output). This pin is labeled as direct because a
secondary transfer is not required to write to this pin.
The GPIO pins are controlled and read in the GPR-D register. The GPR-C register is used to configure the GPIO
pins as input or output pins. The default reset condition is 11111111b, indicating that all are configured as inputs.
For further details on register programming see the register programming section. The DGPO pin does not need
configuring and is controlled by the D1 bit in the SDR data stream (that is, from the DSP to the TLFD500PN)
during primary data transfers. In addition, a secondary transfer is not required to read GPIO0 and GPIO1 when
they are configured as inputs. Their values can be mapped into the lower two bits of the SDX data stream (that
is, from TLFD500PN to DSP) during primary data transfers. To map the values of GPIO0 and GPIO1 into the
lower two bits of the SDX ADC data stream, set the appropriate bit in the MCR register.
For more flexibility, the values of GPIO0 – GPIO7 are mapped into the upper eight data bits of the SDX data
stream on secondary data transfers. This allows the host processor to read the values of the GPIO pins and
the contents of another control register during the same secondary data transfer. When a GPIO pin is being
configured as an output, its corresponding status bit in the SDX data stream will be the last value written to the
output pin.
Each output is capable of driving 2 mA.
reference system
The integrated reference provides voltage and current to the internal analog blocks. It is also brought out to
external pins for noise decoupling. They should not be used as dc voltage source.
When the internal reference is being used by the device, the device may be powered down by writing the
appropriate reference control bit in the main control register (MCR) to achieve power savings during periods
of device inactivity.
auxiliary amplifiers
Four auxiliary high-performance operational amplifiers on the chip allow for additional onboard filtering and
amplification with minimal component count. Each op-amp has differential inputs and outputs, with 2 input pins
and 2 output pins. Each op-amp can be enabled by register programming.
The typical specifications for the operational amplifiers are as follows:
DC Gain:
126 dB
Bandwidth:
116 MHz
PSRR:
100 dB at dc, 70 dB at 1 MHz, and 40 dB at 4 MHz
Output common-mode: AVDD_RX/2 (auxiliary amplifier 3,4) or AVDD_TX/2 (auxiliary amplifier 1,2)
Input interface:
AC coupled
device power-up sequence
All digital and analog supplies must be properly biased. All supply pins are mandatory. The power supply can
not be switched, even when the codec has been powered down or parts of the codec are in power-down mode.
Reset must be held at least 20 µs after power up. To reset the reference circuit and registers requires 100 ms.
When the chip is woken up from hardware power-down mode, it takes100 ms to reset the reference circuit
before the chip works in normal mode. When the chip is woken up from software power-down mode, only 20
µs is needed before valid data comes out (reference must be kept on). Register values will not change in either
wake-up operation.
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