TLFD500 Datasheet, PDF (6/38 Pages) Texas Instruments – 3.3 V INTEGRATED G.LITE ANALOG FRONT END

TLFD500PN
3.3 V INTEGRATED G.LITE ANALOG FRONT END
SLAS207B – JUNE 1999 – REVISED MAY 2000
detailed description (continued)
receive
The receive channel consists of a high-pass filter, a programmable gain amplifier, an ADC, and filters. In
addition, it has an equalizer to attain maximum system performance. The input of the receiver is fully differential.
The ADC in the receive channel is a 14-bit converter which samples at 4.416 Msps for 4X oversampling. An
on-chip decimator reduces the sampling frequency to 1.104 MHz. The low pass filtering of the receive channel
limits the converted data to frequencies below 552 kHz.
The high-pass analog filter is used to reject the near-end echo to maximize the dynamic range of the ADC. The
high-pass filter consists of two stages: (1) a second order high-pass filter (HPF1) and, (2) a third order elliptic
high-pass filter (HPF2). Both stages have a cutoff at 180 kHz. The filter is divided into two stages to minimize
the noise from a single stage being amplified throughout. Together, the two high-pass filters typically attenuate
the echo power by 30 dB. There is a programmable gain amplifier (PGA) between the two filters for coarse gain
adjustments of 0-dB –12-dB in 3-dB steps. After the high-pass filter stage, the receiver channel has a
0-dB –18-dB PGA that can be adjusted in 6-dB steps. HPF2 and PGAs are integrated in one block. Figure 1(a),
1(b), and 1(c) show the frequency response of HPF1 and HPF2 (with PGAs).
The PGA is followed by a 552-kHz low-pass filter with a programmable 25-dB/MHz slope (5-dB/MHz step)
equalizer incorporated. After the equalizer, there is a fine-gain adjustment PGA of 0-dB to 9-dB in 0.25-dB steps.
All the RX PGAs are controlled via the PGA control registers (PCR–RX1 and PCR–RX2). See the register
programming section for details about register programming.
6
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265