TLFD500 Datasheet, PDF (26/38 Pages) Texas Instruments – 3.3 V INTEGRATED G.LITE ANALOG FRONT END

TLFD500PN
3.3 V INTEGRATED G.LITE ANALOG FRONT END
SLAS207B – JUNE 1999 – REVISED MAY 2000
MCR – master control register
Address: 01111b
D7
GP12EN
D6
DLBEN
Contents at reset: 00000000b
D5
D4
D3
ALBEN
SWRST VCDACPD
D2
RXPD
D1
TXPD
D0
SWREFPD
Table 14. MCR Control
D7 D6 D5 D4 D3 D2 D1 D0 REG VALUE
BIT NAME
DESCRIPTION
0
–
–
–
–
–
–
–
1
–
–
–
–
–
–
–
–
0x80
GP12EN
No effect on SDX
Show GPIO 1 and 2 in SDX primary.
–
0
–
–
–
–
–
–
–
1
–
–
–
–
–
–
–
0x40
DLBEN
No effect on digital loop back
Enable digital loop back
–
–
0
–
–
–
–
–
–
–
1
–
–
–
–
–
–
0x20
ALBEN
No effect on analog loop back
Enable analog loop back
–
–
–
0
–
–
–
–
–
–
–
1
–
–
–
–
–
0x10
SWRST
No effect on reset
Perform soft reset
–
–
–
–
0
–
–
–
–
–
–
–
1
–
–
–
–
0x08
VCDACPD
Power up VCXODAC
Power down VCXODAC
–
–
–
–
–
0
–
–
–
–
–
–
–
1
–
–
–
0x04
RXPD
Power up RX channel
Power down RX channel
–
–
–
–
–
–
0
–
–
–
–
–
–
–
1
–
–
0x02
TXPD
Power up TX channel
Power down TX channel
–
–
–
–
–
–
–
0
–
–
–
–
–
–
–
1
–
0x01
SWREFPD
Power up (soft) main reference
Power down (soft) main reference
NOTES: 11. The SWRST and SWREFPD refer to the word software, since the reset is done by register programming as opposed to hard resets
done by forcing pin logic levels.
12. Analog loop-back means looping back of the analog TX output to the RX input. This way the codec can be tested without need of
external analog sources.
13. Digital loop-back means looping back the digital RX output to the TX input. Here we can test the code without the need for a DSP
and serial data transfer.
CAUTION:
All power downs of VCXODAC, RX, and TX channels occur with the reference still on.
DPLL detailed description
The default value of register NCO_DEF is 64. With the 35.328 MHz input clock, the output frequency of the PLL
is 4 × 35.328 = 141.312 MHz. To obtain an ADC clock of 2.208 MHz the divide ratio (controlled by register
NCO_DEF) needs to be 64. Increasing or decreasing this ratio (for example, 65 or 63) can effect a temporary
phase shift. The ratio is controlled by the DSP through register programming.
In DPLL mode, the ADC clock (ADCLK) will work at 2.208 MHz instead of the 4.416 MHz used in the VCXO
mode. The DAC clock (DACLK) will continue to work at 4.416 MHz. When the ADCLK is jittered, the DACLK
is also jittered.
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