TLFD500 Datasheet, PDF (7/38 Pages) Texas Instruments – 3.3 V INTEGRATED G.LITE ANALOG FRONT END

detailed description (continued)
50
TLFD500PN
3.3 V INTEGRATED G.LITE ANALOG FRONT END
SLAS207B – JUNE 1999 – REVISED MAY 2000
2
0
0
–50
–2
–100
–150
–200
–250
0
0.5
1
1.5
f – Frequency – Hz
2
× 105
(a) RX-Stage HPF1 Frequency Response (0 to 200 kHz)
–4
–6
–8
–10
1
1.2
1.4
1.6
1.8
2
f – Frequency – Hz
× 105
(b) RX-Stage HPF1 Frequency Response (100 kHz to 200 kHz)
0
–
–3
–6
9
–12
–15
–18
–21
–24
–27
38.6
90.6
142.
194.
246.
298.
6 _kHz 6
6
6
(c) RX-Stage HPF2 Frequency Response (PGA1 = PGA2 = 0 dB)
Figure 1. RX Stage HPF1 and HPF2 Frequency Response
clock control – VCXO mode
The VCXODAC uses a 12-bit, 2s complement number to control a 0-V to 3-V analog output. The two 8-bit
registers, VCR-M and VCR-L, are used to generate the 12-bit control code (2s complement). This implies the
use of 16 bits to obtain a 12-bit number.
VCR-M register occupy the most significant 8 bits in the 12-bit number and the lower 4 bits of the VCR-L register
(VCR-L[3:0] ) are used for the low 4 bits of the 12-bit number. The 12-bit code is updated every time either
register is updated. VCR-L[7:4] must always be zero.
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