TLFD500 Datasheet, PDF (15/38 Pages) Texas Instruments – 3.3 V INTEGRATED G.LITE ANALOG FRONT END

TLFD500PN
3.3 V INTEGRATED G.LITE ANALOG FRONT END
BCR – bypass control register
SLAS207B – JUNE 1999 – REVISED MAY 2000
Address: 00001b
D7
Reserved
D6
Reserved
Contents at reset: 00000000b
D5
D4
D3
Reserved Reserved
ECHO
D2
TXHPEN
D1
D0
RXHP2PD RXHP1PD
Table 3. EQR Bit Definition
D7 D6 D5 D4 D3 D2 D1 D0 REG. VALUE BIT NAME
DESCRIPTION
R
–
–
–
–
–
–
–
–
Reserved Bit reserved for future use
–
R
–
–
–
–
–
–
–
Reserved Bit reserved for future use
–
–
R
–
–
–
–
–
–
Reserved Bit reserved for future use
–
–
–
R
–
–
–
–
–
Reserved Bit reserved for future use
–
–
–
–
0
–
–
–
–
–
–
–
1
–
–
–
–
0x08
ECHO
Do not echo SDR data on SDX
Echo SDR data on SDX (see Note 1)
–
–
–
–
–
0
–
–
–
–
–
–
–
1
–
–
–
0x04
TXHPEN
Enable TX HP Filter
Bypass TX HP Filter
–
–
–
–
–
–
0
–
–
–
–
–
–
–
1
–
–
0x02
RXHP2PD
Power up RX HP Filter 2
Power down RX HP Filter 2
–
–
–
–
–
–
–
0
–
–
–
–
–
–
–
1
–
0x01
RXHP1PD
Power up RX HP Filter 1
Power down RX HP Filter 1
NOTE 1: ECHO mode allows for a quick verification of the serial interface operation. It sends back the data from input data buffer to the output
data buffer and does not exercise the RX or TX channel.
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
15