TLFD500 Datasheet, PDF (11/38 Pages) Texas Instruments – 3.3 V INTEGRATED G.LITE ANALOG FRONT END

detailed description (continued)
SCLK
(Output)
TLFD500PN
3.3 V INTEGRATED G.LITE ANALOG FRONT END
SLAS207B – JUNE 1999 – REVISED MAY 2000
FSX
(output)
SDX
(Output)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
t1 t2 t3
t1: DSP detects FSX
t2: TLFD500PN sends data
t3: DSP latches data
(a) TLFD500PN to DSP
SCLK
(Output)
FSR
(output)
SDR
(Input)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
t1 t2
t3
t1: DSP detects FSR
t2: DSP sends data
t3: TLFD500PN latches data
(b) DSP to TLFD500PN
NOTE: TI DSP requires 10 ns after the positive edge of the SCLK to give the SDR data. This plus the board delay, output buffer (for SCLK) and
input buffer delay (for SDR) to around 17 ns. As a consequence the SDR data can not be latched at the negative edge of SCLK.
Figure 5. Data Transfers
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