TLFD500 Datasheet, PDF (10/38 Pages) Texas Instruments – 3.3 V INTEGRATED G.LITE ANALOG FRONT END

TLFD500PN
3.3 V INTEGRATED G.LITE ANALOG FRONT END
SLAS207B – JUNE 1999 – REVISED MAY 2000
secondary transfer data mapping (continued)
D15
D9 D8 D7
D0
SDR (Read) 1 A4 A3 A2 A1 A0
Don’t Care
Register Address Don’t Care
D15
D8 D7
D0
SDX (Read)
GPIO0 – 7 Status
Register Data
Read Cycle (Codec Register Data Read by DSP)
D9 D8 D7
D0
SDR (Write) 0 A4 A3 A2 A1 A0
Register Address Don’t Care
Data to the Register
D15
D8 D7
D0
SDX (Write)
GPIO0 – 7 Status
All 0
Write Cycle (DSP Data Write to Codec Register)
Figure 4. Secondary Transfer Data Bit Mapping
example data transfers
Figures 5(a) and 5(b) show the timing relationship for SCLK, FSX, SDX, FSR, and SDR in a primary
communication. The timing sequence for this operation is as follows:
1. FS is set high and remains high during one SCLK period, then returns to low.
2. A 16-bit word is transmitted from the ADC (SDX), and a 16-bit word is received for DAC conversion (SDR).
Figure 6(a) and 6(b) shows the timing relationship with secondary request.
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