TLFD500 Datasheet, PDF (24/38 Pages) Texas Instruments – 3.3 V INTEGRATED G.LITE ANALOG FRONT END

TLFD500PN
3.3 V INTEGRATED G.LITE ANALOG FRONT END
SLAS207B – JUNE 1999 – REVISED MAY 2000
NCO_DIV_DELAY – numerically controlled oscillator delay control register
Address: 01101b
D7
NCDLY[7]
D6
NCDLY[6]
Contents at reset: 00000000b
D5
D4
D3
NCDLY[5] NCDLY[4] NCDLY[3]
D2
NCDLY[2]
D1
NCDLY[1]
D0
NCDLY[0]
Table 12. NCO Default Value
D7 D6 D5 D4 D3 D2 D1 D0 HEX VALUE BIT NAME
0
0
0
0
0
0
0
0
0×00
0
0
0
0
0
0
0
1
0×01
0
0
0
0
0
0
1
0
0×02
NCDLY[7:0]
…
…
…
…
…
…
…
…
0×03 – 0×FD
1
1
1
1
1
1
1
0
0×FE
1
1
1
1
1
1
1
1
0×FF
NOTES: 9. The formula to convert NCDLY[7:0] to delay is straightforward.
Delay (number of ADCLK periods) = NDCLK[7:0] (except for 0 and 1).
10. ADCLK–A/D converter sampling clock
DESCRIPTION
INVALID
INVALID
ADCLK jittered 2 sample clocks (of
ADCLK) after write into the
NCO_DIV_DELAY register (see Note
10)
Jitter after 3 to 253 sample clocks (All
individual values are valid)
Jitter after 254 sample clocks
Jitter after 255 sample clocks
CAUTION:
This register is also the only means of communicating to the codec that the ADCLK must
be jittered. Thus not writing a value implies that jitter will not take place even if other
registers have non-default values. As a side consequence, this register does not remember
its value. All the others store them unless RESET.
Writing 0 or 1 is not recommended
examples:
1. NCDEF[7:0] = 64 (dec.), NCDEL[4:0] = 1, NCRPT[2:0] = 2, NCDLY[7:0] = 5. This shows a default division
value of 64, giving a normal ADCLK of 2.208 MHz (assuming 35.328 MHz input); the division ratio will be
64 + 1 = 65 to effect the jitter, that is, pulling in the clock phase. The jitter will be repeated for 2 consecutive
samples. The jitter will take effect 5 ADCLK sample periods after writing to NCDLY.
2. NCDEF[7:0] = 63 (decimal), NCDEL[4:0] = –1, NCRPT[2:0] = 2, NCDLY[7:0] = 5. Similar to 1. The default
frequency is slightly less than 2.208 MHz. Since the division ratio is 63 – 1 = 62, the clock phase is pushed
out.
3. NCDEF[7:0] = 64 (decimal), NCDEL[4:0] = 0, NCRPT[2:0] = 2, NCDLY[7:0] = 5. Here the jitter will not be
observed, since the delta register is zero.
4. NCDEF[7:0] = 64 (decimal), NCDEL[4:0] = 1, NCRPT[2:0] = 0, NCDLY[7:0] = 5. Here the jitter will not be
observed, since the repeat register is zero.
5. NCDEF[7:0] = 64 (decimal), NCDEL[4:0] = 1, NCRPT[2:0] = 2, NCDLY[7:0] = 0. This is invalid and not
recommended. NCDLY[7:0] can not be 0 or 1.
6. NCDEF[7:0] = 64 (decimal), NCDEL[4:0] = 1, NCRPT[2:0] = 2. Here the jitter will not occur since there was
not writing to NCDLY. The other registers will retain their values as in all other cases.
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