TLFD500 Datasheet, PDF (32/38 Pages) Texas Instruments – 3.3 V INTEGRATED G.LITE ANALOG FRONT END

TLFD500PN
3.3 V INTEGRATED G.LITE ANALOG FRONT END
SLAS207B – JUNE 1999 – REVISED MAY 2000
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
serial port (see Figures 7 and 8) and DGPO (see Figure 9)
PARAMETER
tc1 Period, SCLK
td1 Delay time, FSR high before SCLK↓
td2 Delay time, FSR high after SCLK↓
td3 Delay time, FSX high before SCLK↓
td4 Delay time, FSX high after SCLK↓
td5 Delay time, SDX data valid after SCLK↑
td6 Delay time, GPIO becomes valid after data is sent
tf
Falling time, SCLK change from high to low
th1 Hold time, SDR keep valid after SCLK↑
tr
Rising time, SCLK change from low to high
tsu1 Setup time, SDR valid before SCLK↑
tc1
tr
SCLK
(Output)
tf
td1
td2
MIN TYP MAX UNIT
28.3
ns
7
ns
7
ns
7
ns
7
ns
7 ns
7 ns
4.4 ns
2
ns
4.6 ns
6
ns
FSR
(Output)
SDR
(Input)
SCLK
(Output)
tsu1
th1
D15
D14
D13
D12
D11
Figure 10. Data Transfers From DSP to TLFD500PN
td3
FSX
(Output)
SDX
(Output)
td4
td5
Figure 11. Data Transfers From TLFD500PN to DSP
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