TLFD500 Datasheet, PDF (5/38 Pages) Texas Instruments – 3.3 V INTEGRATED G.LITE ANALOG FRONT END

TLFD500PN
3.3 V INTEGRATED G.LITE ANALOG FRONT END
TERMINAL
NAME
NC
PLLSEL
PWRDN
REFM
REFP
RESET
RXBANDGAP
RXINP
RXINM
SCLK
SDR
SDX
TXBANDGAP
TXOUTP
TXOUTM
VCXOCNTL
VMID_RX
VSS
NO.
36,53, 58,
63
42
17
45
46
38
43
70
71
19
20
18
14
5
6
13
50
80
Terminal Functions (Continued)
SLAS207B – JUNE 1999 – REVISED MAY 2000
I/O
No connection. Keep floating.
DESCRIPTION
I Selects between VCXO mode and DPLL mode. If the pin is tied high PLL mode is selected.
Pin should be tied low for VCXO mode. Cannot be left floating.
I Power-down pin. When PWRDN is pulled low the device goes into power-down mode. The
default state of this pin is low.
O Negative reference filter node. This terminal is provided for low-pass filtering of the internal
band-gap reference. The optimal ceramic capacitor value is 10 µF (tantalum) and 0.1 µF
(ceramic), connected to analog ground. The nominal dc voltage at this terminal is 0.5 V.
O Positive reference filter node. This terminal is provided for low-pass filtering of the internal
band-gap reference. The optimal ceramic capacitor value is 10 µF (tantalum) 0.1 µF
(ceramic), connected to analog ground. The nominal dc voltage at this terminal is 2.5 V.
I Device reset input pin. Initializes all the device’s internal registers to their default values.
The default state of this pin is low.
O RX channel band-gap filter node. This terminal is provided for decoupling of the 1.5-V
band-gap reference. The optimal capacitor value is 10 µF (tantalum) and 0.1 µF (ceramic).
This node should not be used as a voltage source.
I RX channel stage 3 positive input. The input is self-biased at AVDD_RX/2.
I RX channel stage 3 negative input. The input is self-biased at AVDD_RX/2.
O Serial port shift clock (transmit and receive)
I Serial data receive from DSP
O Serial data transmit to DSP
O TX channel band-gap filter node. This terminal is provided for decoupling of the 1.5-V
band-gap reference. The optimal capacitor value is 10 µF (tantalum) and 0.1 µF (ceramic).
This node should not be used as a voltage source.
O TX channel positive output
O TX channel negative output
O DAC output to control onboard VCXO
I/O Decoupling Vmid for ADC. Add 10 µF (tantalum) and 0.1 µF (ceramic) capacitors to analog
ground.
I Substrate. Connect to analog ground.
detailed description
transmit
The transmit channel is powered by a high performance DAC. The transmit channel update rate is 276 kHz.
The DAC is a 14-bit DAC at 4.416-MHz. This provides 16X oversampling. A band-pass filter limits the output
of the transmitter to a frequency range of 30 kHz to 138 kHz. A differential amplifier drives the output into the
external line driver. The differential amplifier has programmable attenuation for added flexibility. The transmitter
high-pass filter can be bypassed by writing the appropriate bit to the filter bypass control register (BCR).
The output spectrum of the DAC complies with the nonoverlapped power spectrum density (PSD) mask
specified in the ITU draft recommendation G.992.2 for G.Lite.
The TXPAA is a programmable-attenuation amplifier. It provides 0 dB to 24 dB of attenuation in1-dB steps. The
TXPAA is controlled via the PAA control register (PCR). For details about register programming see the register
programming section.
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