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DS90UR916Q_13 Datasheet, PDF (9/45 Pages) Texas Instruments – 5 - 65 MHz 24-bit Color FPD-Link II Deserializer with Image Enhancement
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DS90UR916Q
www.ti.com
SNOSB46E – MARCH 2011 – REVISED APRIL 2013
Deserializer DC Electrical Characteristics(1)(2)(3) (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symb
ol
Parameter
Conditions
Pin/Freq.
CML DRIVER OUTPUT DC SPECIFICATIONS – EQ TEST PORT
VOD
Differential Output
Voltage
RL = 100Ω
VOS
Offset Voltage
Single-ended
RL = 100Ω
CMLOUTP,
CMLOUTN
RT
Internal Termination
Resistor
SUPPLY CURRENT
IDD1
IDDIO1
Deserializer
Supply Current
(includes load current)
IDDZ
IDDIOZ
Deserializer Supply
Current Power Down
Checker Board Pattern,
OS_PCLK/DATA = H,
EQ = 001,
SSCG=ON,CMLOUTP/N
enabled
CL = 4pF, Figure 4
PDB = 0V, All other
LVCMOS Inputs = 0V
VDD= 1.89V
VDDIO=1.89V
VDDIO = 3.6V
VDD= 1.89V
VDDIO=1.89V
VDDIO = 3.6V
All VDD pins
VDDIO
All VDD pins
VDDIO
Min Typ Max Units
542
mV
1.4
V
80
100 120
Ω
93 110 mA
33
45
mA
62
75
mA
40 3000 µA
5
50
µA
10 100 µA
Deserializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Pin/Freq.
tRCP
PCLK Output Period
tRDC
PCLK Output Duty Cycle
SSCG=OFF, 5–65MHz
SSCG=ON, 5–20MHz
PCLK
PCLK
SSCG=ON, 20–65MHz
tCLH
LVCMOS
Low-to-High
Transition Time, Figure 5
tCHL
LVCMOS
High-to-Low
Transition Time, Figure 5
tROS
Data Valid before PCLK – Set
Up Time, Figure 9
tROH
Data Valid after PCLK – Hold
Time, Figure 9
tHBLANK
tDDLT
Horizontal Blanking Time
Deserializer Lock Time,
Figure 8
VDDIO = 1.8V
CL = 4 pF (lumped load)
VDDIO = 3.3V
CL = 4 pF (lumped load)
VDDIO = 1.8V
CL = 4 pF (lumped load)
VDDIO = 3.3V
CL = 4 pF (lumped load)
VDDIO = 1.71 to 1.89V or
3.0 to 3.6V
CL = 4 pF (lumped load)
VDDIO = 1.71 to 1.89V or
3.0 to 3.6V
CL = 4 pF (lumped load)
SSC[3:0] = 0000 (OFF)(1)
SSC[3:0] = 0000 (OFF)(1)
SSC[3:0] = ON(1)
SSC[3:0] = ON(1)
PCLK/RGB[7:0], HS, VS,
DE
PCLK/RGB[7:0], HS, VS,
DE
RGB[7:0], HS, VS, DE
RGB[7:0], HS, VS, DE
HS
PCLK = 5 MHz
PCLK = 65MHz
PCLK = 5MHz
PCLK = 65MHz
tDD
tDPJ (2)
Des Delay - Latency, Figure 6
Des Period Jitter
SSC[3:0] = OFF(3)(4)
PCLK = 5 MHz
PCLK = 10 MHz
PCLK = 65 MHz
Min
15.38
43
35
40
0.27
0.4
6
Typ
Max Units
T
200
ns
50
57
%
59
65
%
53
60
%
2.1
ns
2.0
ns
1.6
ns
1.5
ns
0.45
T
0.55
T
tRCP
3
ms
4
ms
30
ms
6
ms
139*T 140*T ns
975 1700 ps
500 1000 ps
550 1250 ps
(1) tPLD and tDDLT is the time required by the serializer and deserializer to obtain lock when exiting power-down state with an active PCLK.
(2) Specification is ensured by design and is not tested in production.
(3) tDPJ is the maximum amount the period is allowed to deviate over many samples.
(4) Specification is ensured by characterization and is not tested in production.
Copyright © 2011–2013, Texas Instruments Incorporated
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